X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=include%2Fconfigs%2Funiphier.h;h=056259849976188fa041b68dce90b67097decca9;hb=9e39003e7ffa327adaef468840196de2e8820d2f;hp=5a53c506c35f50be969b4e5188d002206910ccfc;hpb=7a7ffedabd29adde9cb6ebe6066256c4cf8b77af;p=people%2Fms%2Fu-boot.git diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 5a53c506c3..0562598499 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -1,6 +1,5 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2012-2015 Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,58 +9,10 @@ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ -#if defined(CONFIG_MACH_PH1_PRO4) -#define CONFIG_DDR_NUM_CH0 2 -#define CONFIG_DDR_NUM_CH1 2 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x20000000 -#define CONFIG_SDRAM1_BASE 0xa0000000 -#define CONFIG_SDRAM1_SIZE 0x20000000 -#endif - -#if defined(CONFIG_MACH_PH1_LD4) -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 -#endif - -#if defined(CONFIG_MACH_PH1_SLD8) -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 -#endif - -/* - * Support card address map - */ -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) -# define CONFIG_SUPPORT_CARD_BASE 0x03f00000 -# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) -# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) -#endif - -#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) -# define CONFIG_SUPPORT_CARD_BASE 0x08000000 -# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630) -# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000) -#endif +#define CONFIG_I2C_EEPROM +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 #ifdef CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE #define CONFIG_SYS_NS16550_CLK 12288000 #define CONFIG_SYS_NS16550_REG_SIZE -2 @@ -74,11 +25,10 @@ #define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE +/* dummy: referenced by examples/standalone/smc911x_eeprom.c */ +#define CONFIG_SMC911X_BASE 0 #define CONFIG_SMC911X_32_BIT -#define CONFIG_SYS_MALLOC_F_LEN 0x2000 - /*----------------------------------------------------------------------- * MMU and Cache Setting *----------------------------------------------------------------------*/ @@ -87,11 +37,15 @@ /* #define CONFIG_SYS_ICACHE_OFF */ /* #define CONFIG_SYS_DCACHE_OFF */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* Comment out the following to enable L2 cache */ #define CONFIG_UNIPHIER_L2CACHE_ON #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_MISC_INIT_F +#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_BOARD_LATE_INIT @@ -122,12 +76,11 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 /* serial console configuration */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_GENERIC_BOARD #if !defined(CONFIG_SPL_BUILD) #define CONFIG_USE_ARCH_MEMSET @@ -173,8 +126,13 @@ #define CONFIG_NAND_DENALI_ECC_SIZE 1024 +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3 +#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 +#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 +#else #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 +#endif #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) @@ -183,28 +141,21 @@ /* USB */ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION -#define CONFIG_CMD_DM - /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " /* * Network Configuration */ -#define CONFIG_ETHADDR 00:21:83:24:00:00 #define CONFIG_SERVERIP 192.168.11.1 #define CONFIG_IPADDR 192.168.11.10 #define CONFIG_GATEWAYIP 192.168.11.1 @@ -212,7 +163,6 @@ #define CONFIG_LOADADDR 0x84000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_BOOTFILE "fit.itb" #define CONFIG_CMDLINE_EDITING /* add command line history */ @@ -225,63 +175,78 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ "tftpboot; bootm;" -#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "image_offset=0x00080000\0" \ - "image_size=0x00f00000\0" \ - "verify=n\0" \ - "norboot=run add_default_bootargs;" \ - "bootm $image_offset\0" \ - "nandboot=run add_default_bootargs;" \ - "nand read $loadaddr $image_offset $image_size;" \ - "bootm\0" \ - "add_default_bootargs=setenv bootargs $bootargs" \ - " console=ttyS0,$baudrate\0" \ +#ifdef CONFIG_FIT +#define CONFIG_BOOTFILE "fitImage" +#define LINUXBOOT_ENV_SETTINGS \ + "fit_addr=0x00100000\0" \ + "fit_addr_r=0x84100000\0" \ + "fit_size=0x00f00000\0" \ + "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ + "bootm $fit_addr\0" \ + "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ + "bootm $fit_addr_r\0" \ + "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ + "bootm $fit_addr_r\0" +#else +#define CONFIG_BOOTFILE "uImage" +#define LINUXBOOT_ENV_SETTINGS \ + "fdt_addr=0x00100000\0" \ + "fdt_addr_r=0x84100000\0" \ + "fdt_size=0x00008000\0" \ + "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "kernel_addr=0x00200000\0" \ + "kernel_addr_r=0x84200000\0" \ + "kernel_size=0x00800000\0" \ + "ramdisk_addr=0x00a00000\0" \ + "ramdisk_addr_r=0x84a00000\0" \ + "ramdisk_size=0x00600000\0" \ + "ramdisk_file=rootfs.cpio.uboot\0" \ + "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ + "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ + "setexpr fdt_addr $nor_base + $fdt_addr &&" \ + "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ + "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ + "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ + "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ + "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ + "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ + "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ + "tftpboot $fdt_addr_r $fdt_file &&" \ + "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "verify=n\0" \ + "norbase=0x42000000\0" \ + "nandupdate=nand erase 0 0x00100000 &&" \ + "tftpboot u-boot-spl-dtb.bin &&" \ + "nand write $loadaddr 0 0x00010000 &&" \ + "tftpboot u-boot-dtb.img &&" \ + "nand write $loadaddr 0x00010000 0x000f0000\0" \ + LINUXBOOT_ENV_SETTINGS /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT -#define CONFIG_HAVE_ARM_SECURE - -/* Memory Size & Mapping */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE - -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE -/* Thre is no memory hole */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE) -#else +#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE) -#endif - -#define CONFIG_SYS_TEXT_BASE 0x84000000 -#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 -#endif -#if defined(CONFIG_MACH_PH1_PRO4) +#else #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -#define CONFIG_BOARD_POSTCLK_INIT - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000) -#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000) +#define CONFIG_SPL_STACK (0x0ff08000) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000) -#else -#define CONFIG_SYS_INIT_SP_ADDR ((CONFIG_SYS_TEXT_BASE) - 0x00001000) -#endif +#define CONFIG_PANIC_HANG #define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ @@ -291,4 +256,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 +#define CONFIG_SPL_MAX_FOOTPRINT 0x10000 + #endif /* __CONFIG_UNIPHIER_COMMON_H__ */