X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=include%2Fgdsys_fpga.h;h=bb8e144e04900f41bd6dd94c85410763adcf7b39;hb=a5a37567c4f7bd6faf85ef4b720f6efce3e8bbbf;hp=1fccd27cc02f16ffa93532b45be1533b0868e49a;hpb=2da0fc0d0fcdd991220cc120e5bc6d44991a5987;p=people%2Fms%2Fu-boot.git

diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 1fccd27cc0..bb8e144e04 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -2,58 +2,93 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __GDSYS_FPGA_H
 #define __GDSYS_FPGA_H
 
+int init_func_fpga(void);
+
 enum {
 	FPGA_STATE_DONE_FAILED = 1 << 0,
 	FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+	FPGA_STATE_PLATFORM = 1 << 2,
 };
 
 int get_fpga_state(unsigned dev);
-void print_fpga_state(unsigned dev);
 
-typedef struct ihs_gpio {
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
+
+extern struct ihs_fpga *fpga_ptr[];
+
+#define FPGA_SET_REG(ix, fld, val) \
+	fpga_set_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+
+#define FPGA_GET_REG(ix, fld, val) \
+	fpga_get_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+
+struct ihs_gpio {
 	u16 read;
 	u16 clear;
 	u16 set;
-} ihs_gpio_t;
+};
 
-typedef struct ihs_i2c {
-	u16 write_mailbox;
+struct ihs_i2c {
+	u16 interrupt_status;
+	u16 interrupt_enable;
 	u16 write_mailbox_ext;
-	u16 read_mailbox;
+	u16 write_mailbox;
 	u16 read_mailbox_ext;
-} ihs_i2c_t;
+	u16 read_mailbox;
+};
 
-typedef struct ihs_osd {
+struct ihs_osd {
 	u16 version;
 	u16 features;
 	u16 control;
 	u16 xy_size;
-} ihs_osd_t;
+	u16 xy_scale;
+	u16 x_pos;
+	u16 y_pos;
+};
+
+struct ihs_mdio {
+	u16 control;
+	u16 address_data;
+	u16 rx_data;
+};
+
+struct ihs_io_ep {
+	u16 transmit_data;
+	u16 rx_tx_control;
+	u16 receive_data;
+	u16 rx_tx_status;
+	u16 reserved;
+	u16 device_address;
+	u16 target_address;
+};
+
+#ifdef CONFIG_NEO
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[8187];	/* 0x0008 */
+	u16 reflection_high;	/* 0x3ffe */
+};
+#endif
 
 #ifdef CONFIG_IO
-typedef struct ihs_fpga {
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_features;	/* 0x0004 */
@@ -62,47 +97,199 @@ typedef struct ihs_fpga {
 	u16 quad_serdes_reset;	/* 0x0012 */
 	u16 reserved_1[8181];	/* 0x0014 */
 	u16 reflection_high;	/* 0x3ffe */
-} ihs_fpga_t;
+};
+#endif
+
+#ifdef CONFIG_IO64
+struct ihs_fpga_channel {
+	u16 status_int;
+	u16 config_int;
+	u16 switch_connect_config;
+	u16 tx_destination;
+};
+
+struct ihs_fpga_hicb {
+	u16 status_int;
+	u16 config_int;
+};
+
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[5];	/* 0x0008 */
+	u16 quad_serdes_reset;	/* 0x0012 */
+	u16 reserved_1[502];	/* 0x0014 */
+	struct ihs_fpga_channel ch[32];		/* 0x0400 */
+	struct ihs_fpga_channel hicb_ch[32];	/* 0x0500 */
+	u16 reserved_2[7487];	/* 0x0580 */
+	u16 reflection_high;	/* 0x3ffe */
+};
 #endif
 
 #ifdef CONFIG_IOCON
-typedef struct ihs_fpga {
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[1];	/* 0x0008 */
+	u16 top_interrupt;	/* 0x000a */
+	u16 reserved_1[4];	/* 0x000c */
+	struct ihs_gpio gpio;	/* 0x0014 */
+	u16 mpc3w_control;	/* 0x001a */
+	u16 reserved_2[2];	/* 0x001c */
+	struct ihs_io_ep ep;	/* 0x0020 */
+	u16 reserved_3[9];	/* 0x002e */
+	struct ihs_i2c i2c0;	/* 0x0040 */
+	u16 reserved_4[10];	/* 0x004c */
+	u16 mc_int;		/* 0x0060 */
+	u16 mc_int_en;		/* 0x0062 */
+	u16 mc_status;		/* 0x0064 */
+	u16 mc_control;		/* 0x0066 */
+	u16 mc_tx_data;		/* 0x0068 */
+	u16 mc_tx_address;	/* 0x006a */
+	u16 mc_tx_cmd;		/* 0x006c */
+	u16 mc_res;		/* 0x006e */
+	u16 mc_rx_cmd_status;	/* 0x0070 */
+	u16 mc_rx_data;		/* 0x0072 */
+	u16 reserved_5[69];	/* 0x0074 */
+	u16 reflection_high;	/* 0x00fe */
+	struct ihs_osd osd0;	/* 0x0100 */
+	u16 reserved_6[889];	/* 0x010e */
+	u16 videomem0[2048];	/* 0x0800 */
+};
+#endif
+
+#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_version;	/* 0x0004 */
 	u16 fpga_features;	/* 0x0006 */
-	u16 reserved_0[6];	/* 0x0008 */
-	ihs_gpio_t gpio;	/* 0x0014 */
+	u16 reserved_0[1];	/* 0x0008 */
+	u16 top_interrupt;	/* 0x000a */
+	u16 reserved_1[2];	/* 0x000c */
+	u16 control;		/* 0x0010 */
+	u16 extended_control;	/* 0x0012 */
+	struct ihs_gpio gpio;	/* 0x0014 */
 	u16 mpc3w_control;	/* 0x001a */
-	u16 reserved_1[19];	/* 0x001c */
-	u16 videocontrol;	/* 0x0042 */
-	u16 reserved_2[93];	/* 0x0044 */
+	u16 reserved_2[2];	/* 0x001c */
+	struct ihs_io_ep ep;	/* 0x0020 */
+	u16 reserved_3[9];	/* 0x002e */
+	struct ihs_i2c i2c0;	/* 0x0040 */
+	u16 reserved_4[10];	/* 0x004c */
+	u16 mc_int;		/* 0x0060 */
+	u16 mc_int_en;		/* 0x0062 */
+	u16 mc_status;		/* 0x0064 */
+	u16 mc_control;		/* 0x0066 */
+	u16 mc_tx_data;		/* 0x0068 */
+	u16 mc_tx_address;	/* 0x006a */
+	u16 mc_tx_cmd;		/* 0x006c */
+	u16 mc_res;		/* 0x006e */
+	u16 mc_rx_cmd_status;	/* 0x0070 */
+	u16 mc_rx_data;		/* 0x0072 */
+	u16 reserved_5[69];	/* 0x0074 */
 	u16 reflection_high;	/* 0x00fe */
-	ihs_osd_t osd;		/* 0x0100 */
-	u16 reserved_3[892];	/* 0x0108 */
-	u16 videomem;		/* 0x0800 */
-} ihs_fpga_t;
+	struct ihs_osd osd0;	/* 0x0100 */
+#ifdef CONFIG_SYS_OSD_DH
+	u16 reserved_6[57];	/* 0x010e */
+	struct ihs_osd osd1;	/* 0x0180 */
+	u16 reserved_7[9];	/* 0x018e */
+	struct ihs_i2c i2c1;	/* 0x01a0 */
+	u16 reserved_8[1834];	/* 0x01ac */
+	u16 videomem0[2048];	/* 0x1000 */
+	u16 videomem1[2048];	/* 0x2000 */
+#else
+	u16 reserved_6[889];	/* 0x010e */
+	u16 videomem0[2048];	/* 0x0800 */
+#endif
+};
+#endif
+
+#ifdef CONFIG_STRIDER_CPU
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[1];	/* 0x0008 */
+	u16 top_interrupt;	/* 0x000a */
+	u16 reserved_1[3];	/* 0x000c */
+	u16 extended_control;	/* 0x0012 */
+	struct ihs_gpio gpio;	/* 0x0014 */
+	u16 mpc3w_control;	/* 0x001a */
+	u16 reserved_2[2];	/* 0x001c */
+	struct ihs_io_ep ep;	/* 0x0020 */
+	u16 reserved_3[9];	/* 0x002e */
+	u16 mc_int;		/* 0x0040 */
+	u16 mc_int_en;		/* 0x0042 */
+	u16 mc_status;		/* 0x0044 */
+	u16 mc_control;		/* 0x0046 */
+	u16 mc_tx_data;		/* 0x0048 */
+	u16 mc_tx_address;	/* 0x004a */
+	u16 mc_tx_cmd;		/* 0x004c */
+	u16 mc_res;		/* 0x004e */
+	u16 mc_rx_cmd_status;	/* 0x0050 */
+	u16 mc_rx_data;		/* 0x0052 */
+	u16 reserved_4[62];	/* 0x0054 */
+	struct ihs_i2c i2c0;	/* 0x00d0 */
+};
+#endif
+
+#ifdef CONFIG_STRIDER_CON
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[1];	/* 0x0008 */
+	u16 top_interrupt;	/* 0x000a */
+	u16 reserved_1[4];	/* 0x000c */
+	struct ihs_gpio gpio;	/* 0x0014 */
+	u16 mpc3w_control;	/* 0x001a */
+	u16 reserved_2[2];	/* 0x001c */
+	struct ihs_io_ep ep;	/* 0x0020 */
+	u16 reserved_3[9];	/* 0x002e */
+	struct ihs_i2c i2c0;	/* 0x0040 */
+	u16 reserved_4[10];	/* 0x004c */
+	u16 mc_int;		/* 0x0060 */
+	u16 mc_int_en;		/* 0x0062 */
+	u16 mc_status;		/* 0x0064 */
+	u16 mc_control;		/* 0x0066 */
+	u16 mc_tx_data;		/* 0x0068 */
+	u16 mc_tx_address;	/* 0x006a */
+	u16 mc_tx_cmd;		/* 0x006c */
+	u16 mc_res;		/* 0x006e */
+	u16 mc_rx_cmd_status;	/* 0x0070 */
+	u16 mc_rx_data;		/* 0x0072 */
+	u16 reserved_5[70];	/* 0x0074 */
+	struct ihs_osd osd0;	/* 0x0100 */
+	u16 reserved_6[889];	/* 0x010e */
+	u16 videomem0[2048];	/* 0x0800 */
+};
 #endif
 
 #ifdef CONFIG_DLVISION_10G
-typedef struct ihs_fpga {
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_version;	/* 0x0004 */
 	u16 fpga_features;	/* 0x0006 */
 	u16 reserved_0[10];	/* 0x0008 */
 	u16 extended_interrupt; /* 0x001c */
-	u16 reserved_1[9];	/* 0x001e */
-	ihs_i2c_t i2c;		/* 0x0030 */
-	u16 reserved_2[35];	/* 0x0038 */
-	u16 reflection_high;	/* 0x007e */
-	u16 reserved_3[15];	/* 0x0080 */
-	u16 videocontrol;	/* 0x009e */
-	u16 reserved_4[176];	/* 0x00a0 */
-	ihs_osd_t osd;		/* 0x0200 */
-	u16 reserved_5[764];	/* 0x0208 */
-	u16 videomem;		/* 0x0800 */
-} ihs_fpga_t;
+	u16 reserved_1[29];	/* 0x001e */
+	u16 mpc3w_control;	/* 0x0058 */
+	u16 reserved_2[3];	/* 0x005a */
+	struct ihs_i2c i2c0;	/* 0x0060 */
+	u16 reserved_3[2];	/* 0x006c */
+	struct ihs_i2c i2c1;	/* 0x0070 */
+	u16 reserved_4[194];	/* 0x007c */
+	struct ihs_osd osd0;	/* 0x0200 */
+	u16 reserved_5[761];	/* 0x020e */
+	u16 videomem0[2048];	/* 0x0800 */
+};
 #endif
 
 #endif