X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=include%2Fpci.h;h=7adc04301c06a90f582622d26bb17f770781a699;hb=f1754f08102781f855370c7d47db0e3d85da5694;hp=d0d152c00bf46c9ee9a1adbcdf06f0fa284b8f24;hpb=82d72a1b9967cff4908f22c57536c3660f794401;p=people%2Fms%2Fu-boot.git diff --git a/include/pci.h b/include/pci.h index d0d152c00b..7adc04301c 100644 --- a/include/pci.h +++ b/include/pci.h @@ -700,6 +700,7 @@ extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus); extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); +extern struct pci_controller *pci_get_hose_head(void); extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); @@ -753,6 +754,10 @@ int pci_last_busno(void); extern void pci_mpc85xx_init (struct pci_controller *hose); #endif +#ifdef CONFIG_PCIE_IMX +extern void imx_pcie_remove(void); +#endif + #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) /** * pci_write_bar32() - Write the address of a BAR including control bits @@ -1007,6 +1012,7 @@ int dm_pci_hose_probe_bus(struct udevice *bus); * * @bus: Bus to read from * @bdf: PCI device address: bus, device and function -see PCI_BDF() + * @offset: Register offset to read * @valuep: Place to put the returned value * @size: Access size * @return 0 if OK, -ve on error @@ -1019,6 +1025,7 @@ int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, * * @bus: Bus to write from * @bdf: PCI device address: bus, device and function -see PCI_BDF() + * @offset: Register offset to write * @value: Value to write * @size: Access size * @return 0 if OK, -ve on error @@ -1026,6 +1033,21 @@ int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, unsigned long value, enum pci_size_t size); +/** + * pci_bus_clrset_config32() - Update a configuration value for a device + * + * The register at @offset is updated to (oldvalue & ~clr) | set. + * + * @bus: Bus to access + * @bdf: PCI device address: bus, device and function -see PCI_BDF() + * @offset: Register offset to update + * @clr: Bits to clear + * @set: Bits to set + * @return 0 if OK, -ve on error + */ +int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, + u32 clr, u32 set); + /** * Driver model PCI config access functions. Use these in preference to others * when you have a valid device @@ -1044,12 +1066,76 @@ int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); +/** + * These permit convenient read/modify/write on PCI configuration. The + * register is updated to (oldvalue & ~clr) | set. + */ +int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); +int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); +int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); + /* * The following functions provide access to the above without needing the * size parameter. We are trying to encourage the use of the 8/16/32-style * functions, rather than byte/word/dword. But both are supported. */ int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); +int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); +int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); +int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); +int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); +int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); + +/** + * pci_generic_mmap_write_config() - Generic helper for writing to + * memory-mapped PCI configuration space. + * @bus: Pointer to the PCI bus + * @addr_f: Callback for calculating the config space address + * @bdf: Identifies the PCI device to access + * @offset: The offset into the device's configuration space + * @value: The value to write + * @size: Indicates the size of access to perform + * + * Write the value @value of size @size from offset @offset within the + * configuration space of the device identified by the bus, device & function + * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is + * responsible for calculating the CPU address of the respective configuration + * space offset. + * + * Return: 0 on success, else -EINVAL + */ +int pci_generic_mmap_write_config( + struct udevice *bus, + int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), + pci_dev_t bdf, + uint offset, + ulong value, + enum pci_size_t size); + +/** + * pci_generic_mmap_read_config() - Generic helper for reading from + * memory-mapped PCI configuration space. + * @bus: Pointer to the PCI bus + * @addr_f: Callback for calculating the config space address + * @bdf: Identifies the PCI device to access + * @offset: The offset into the device's configuration space + * @valuep: A pointer at which to store the read value + * @size: Indicates the size of access to perform + * + * Read a value of size @size from offset @offset within the configuration + * space of the device identified by the bus, device & function numbers in @bdf + * on the PCI bus @bus. The callback function @addr_f is responsible for + * calculating the CPU address of the respective configuration space offset. + * + * Return: 0 on success, else -EINVAL + */ +int pci_generic_mmap_read_config( + struct udevice *bus, + int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), + pci_dev_t bdf, + uint offset, + ulong *valuep, + enum pci_size_t size); #ifdef CONFIG_DM_PCI_COMPAT /* Compatibility with old naming */ @@ -1059,8 +1145,6 @@ static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, return pci_write_config32(pcidev, offset, value); } -int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); - /* Compatibility with old naming */ static inline int pci_write_config_word(pci_dev_t pcidev, int offset, u16 value) @@ -1068,8 +1152,6 @@ static inline int pci_write_config_word(pci_dev_t pcidev, int offset, return pci_write_config16(pcidev, offset, value); } -int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); - /* Compatibility with old naming */ static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, u8 value) @@ -1077,8 +1159,6 @@ static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, return pci_write_config8(pcidev, offset, value); } -int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, u32 *valuep) @@ -1086,8 +1166,6 @@ static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, return pci_read_config32(pcidev, offset, valuep); } -int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_word(pci_dev_t pcidev, int offset, u16 *valuep) @@ -1095,15 +1173,12 @@ static inline int pci_read_config_word(pci_dev_t pcidev, int offset, return pci_read_config16(pcidev, offset, valuep); } -int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, u8 *valuep) { return pci_read_config8(pcidev, offset, valuep); } - #endif /* CONFIG_DM_PCI_COMPAT */ /** @@ -1243,9 +1318,9 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) #define dm_pci_virt_to_io(dev, addr) \ - dm_dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) + dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ - dm_dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) + dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) /** * dm_pci_find_device() - find a device by vendor/device ID