X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=ls-ecaps.c;h=55059480ee7a417bf5311a60e042e15babdcb375;hb=d9b702cde8550b245defa130f3d93a5b34ae68d7;hp=7888214d5c9db42a65fc95f5c0c04f193e9cf733;hpb=d61c47722516d1955c4e7176d738b54a762f9343;p=thirdparty%2Fpciutils.git diff --git a/ls-ecaps.c b/ls-ecaps.c index 7888214..5505948 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -1,7 +1,7 @@ /* * The PCI Utilities -- Show Extended Capabilities * - * Copyright (c) 1997--2008 Martin Mares + * Copyright (c) 1997--2010 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ @@ -11,6 +11,71 @@ #include "lspci.h" +static void +cap_tph(struct device *d, int where) +{ + u32 tph_cap; + printf("Transaction Processing Hints\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4)) + return; + + tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES); + + if (tph_cap & PCI_TPH_INTVEC_SUP) + printf("\t\tInterrupt vector mode supported\n"); + if (tph_cap & PCI_TPH_DEV_SUP) + printf("\t\tDevice specific mode supported\n"); + if (tph_cap & PCI_TPH_EXT_REQ_SUP) + printf("\t\tExtended requester support\n"); + + switch (tph_cap & PCI_TPH_ST_LOC_MASK) { + case PCI_TPH_ST_NONE: + printf("\t\tNo steering table available\n"); + break; + case PCI_TPH_ST_CAP: + printf("\t\tSteering table in TPH capability structure\n"); + break; + case PCI_TPH_ST_MSIX: + printf("\t\tSteering table in MSI-X table\n"); + break; + default: + printf("\t\tReserved steering table location\n"); + break; + } +} + +static u32 +cap_ltr_scale(u8 scale) +{ + return 1 << (scale * 5); +} + +static void +cap_ltr(struct device *d, int where) +{ + u32 scale; + u16 snoop, nosnoop; + printf("Latency Tolerance Reporting\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4)) + return; + + snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP); + scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); + printf("\t\tMax snoop latency: %lldns\n", + ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale); + + nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP); + scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); + printf("\t\tMax no snoop latency: %lldns\n", + ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale); +} + static void cap_dsn(struct device *d, int where) { @@ -25,15 +90,16 @@ cap_dsn(struct device *d, int where) } static void -cap_aer(struct device *d, int where) +cap_aer(struct device *d, int where, int type) { - u32 l; + u32 l, l0, l1, l2, l3; + u16 w; printf("Advanced Error Reporting\n"); if (verbose < 2) return; - if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24)) + if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40)) return; l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS); @@ -58,18 +124,87 @@ cap_aer(struct device *d, int where) FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); l = get_conf_long(d, where + PCI_ERR_COR_STATUS); - printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n", + printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n", FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); l = get_conf_long(d, where + PCI_ERR_COR_MASK); - printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n", + printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n", FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); l = get_conf_long(d, where + PCI_ERR_CAP); - printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n", + printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n" + "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n", PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE), - FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE)); + FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE), + FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE), + FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG)); + + l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG); + l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4); + l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8); + l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12); + printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3); + + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) + { + if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12)) + return; + + l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND); + printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n", + FLAG(l, PCI_ERR_ROOT_CMD_COR_EN), + FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN), + FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN)); + + l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS); + printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n" + "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n", + FLAG(l, PCI_ERR_ROOT_COR_RCV), + FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV), + FLAG(l, PCI_ERR_ROOT_UNCOR_RCV), + FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV), + FLAG(l, PCI_ERR_ROOT_FIRST_FATAL), + FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV), + FLAG(l, PCI_ERR_ROOT_FATAL_RCV), + PCI_ERR_MSG_NUM(l)); + + w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC); + printf("\t\tErrorSrc: ERR_COR: %04x ", w); + + w = get_conf_word(d, where + PCI_ERR_ROOT_SRC); + printf("ERR_FATAL/NONFATAL: %04x\n", w); + } +} + +static void cap_dpc(struct device *d, int where) +{ + u16 l; + printf("Downstream Port Containment\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_DPC_CAP, 8)) + return; + + l = get_conf_word(d, where + PCI_DPC_CAP); + printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", + PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK), + FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR)); + + l = get_conf_word(d, where + PCI_DPC_CTL); + printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n", + PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT), + FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER), + FLAG(l, PCI_DPC_CTL_DL_ACTIVE)); + + l = get_conf_word(d, where + PCI_DPC_STATUS); + printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n", + FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT), + FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l)); + + l = get_conf_word(d, where + PCI_DPC_SOURCE); + printf("\t\tSource:\t%04x\n", l); } static void @@ -139,6 +274,54 @@ cap_ats(struct device *d, int where) FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w)); } +static void +cap_pri(struct device *d, int where) +{ + u16 w; + u32 l; + + printf("Page Request Interface (PRI)\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc)) + return; + + w = get_conf_word(d, where + PCI_PRI_CTRL); + printf("\t\tPRICtl: Enable%c Reset%c\n", + FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET)); + w = get_conf_word(d, where + PCI_PRI_STATUS); + printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n", + FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI), + FLAG(w, PCI_PRI_STATUS_STOPPED)); + l = get_conf_long(d, where + PCI_PRI_MAX_REQ); + printf("\t\tPage Request Capacity: %08x, ", l); + l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ); + printf("Page Request Allocation: %08x\n", l); +} + +static void +cap_pasid(struct device *d, int where) +{ + u16 w; + + printf("Process Address Space ID (PASID)\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_PASID_CAP, 4)) + return; + + w = get_conf_word(d, where + PCI_PASID_CAP); + printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n", + FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV), + PCI_PASID_CAP_WIDTH(w)); + w = get_conf_word(d, where + PCI_PASID_CTRL); + printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n", + FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC), + FLAG(w, PCI_PASID_CTRL_PRIV)); +} + static void cap_sriov(struct device *d, int where) { @@ -213,8 +396,320 @@ cap_sriov(struct device *d, int where) PCI_IOV_MSA_BIR(l)); } +static void +cap_vc(struct device *d, int where) +{ + u32 cr1, cr2; + u16 ctrl, status; + int evc_cnt; + int arb_table_pos; + int i, j; + static const char ref_clocks[][6] = { "100ns" }; + static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" }; + static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" }; + char buf[8]; + + printf("Virtual Channel\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + 4, 0x1c - 4)) + return; + + cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1); + cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2); + ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL); + status = get_conf_word(d, where + PCI_VC_PORT_STATUS); + + evc_cnt = BITS(cr1, 0, 3); + printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n", + BITS(cr1, 4, 3), + TABLE(ref_clocks, BITS(cr1, 8, 2), buf), + 1 << BITS(cr1, 10, 2)); + + printf("\t\tArb:"); + for (i=0; i<8; i++) + if (arb_selects[i][0] != '?' || cr2 & (1 << i)) + printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i)); + arb_table_pos = BITS(cr2, 24, 8); + + printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf)); + printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1)); + + if (arb_table_pos) + { + arb_table_pos = where + 16*arb_table_pos; + printf("\t\tPort Arbitration Table [%x] \n", arb_table_pos); + } + + for (i=0; i<=evc_cnt; i++) + { + int pos = where + PCI_VC_RES_CAP + 12*i; + u32 rcap, rctrl; + u16 rstatus; + int pat_pos; + + printf("\t\tVC%d:\t", i); + if (!config_fetch(d, pos, 12)) + { + printf("\n"); + continue; + } + rcap = get_conf_long(d, pos); + rctrl = get_conf_long(d, pos+4); + rstatus = get_conf_word(d, pos+10); + + pat_pos = BITS(rcap, 24, 8); + printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n", + pat_pos, + BITS(rcap, 16, 6) + 1, + FLAG(rcap, 1 << 15)); + + printf("\t\t\tArb:"); + for (j=0; j<8; j++) + if (vc_arb_selects[j][0] != '?' || rcap & (1 << j)) + printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j)); + + printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n", + FLAG(rctrl, 1 << 31), + BITS(rctrl, 24, 3), + TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf), + BITS(rctrl, 0, 8)); + + printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n", + FLAG(rstatus, 2), + FLAG(rstatus, 1)); + + if (pat_pos) + printf("\t\t\tPort Arbitration Table \n"); + } +} + +static void +cap_rclink(struct device *d, int where) +{ + u32 esd; + int num_links; + int i; + static const char elt_types[][9] = { "Config", "Egress", "Internal" }; + char buf[8]; + + printf("Root Complex Link\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4)) + return; + + esd = get_conf_long(d, where + PCI_RCLINK_ESD); + num_links = BITS(esd, 8, 8); + printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n", + BITS(esd, 24, 8), + BITS(esd, 16, 8), + TABLE(elt_types, BITS(esd, 0, 8), buf)); + + for (i=0; i\n"); + return; + } + desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC); + addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR); + addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4); + + printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n", + BITS(desc, 24, 8), + BITS(desc, 16, 8), + FLAG(desc, 4), + ((desc & 2) ? "Config" : "MemMapped"), + FLAG(desc, 1)); + + if (desc & 2) + { + int n = addr_lo & 7; + if (!n) + n = 8; + printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n", + BITS(addr_lo, 20, n), + BITS(addr_lo, 15, 5), + BITS(addr_lo, 12, 3), + addr_hi, addr_lo); + } + else + printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo); + } +} + +static void +cap_evendor(struct device *d, int where) +{ + u32 hdr; + + printf("Vendor Specific Information: "); + if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4)) + { + printf("\n"); + return; + } + + hdr = get_conf_long(d, where + PCI_EVNDR_HEADER); + printf("ID=%04x Rev=%d Len=%03x \n", + BITS(hdr, 0, 16), + BITS(hdr, 16, 4), + BITS(hdr, 20, 12)); +} + +static int l1pm_calc_pwron(int scale, int value) +{ + switch (scale) + { + case 0: + return 2 * value; + case 1: + return 10 * value; + case 2: + return 100 * value; + } + return -1; +} + +static void +cap_l1pm(struct device *d, int where) +{ + u32 l1_cap, val, scale; + int time; + + printf("L1 PM Substates\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12)) + { + printf("\t\t\n"); + return; + } + + l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP); + printf("\t\tL1SubCap: "); + printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n", + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + { + printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8)); + time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5)); + if (time != -1) + printf("PortTPowerOnTime=%dus\n", time); + else + printf("PortTPowerOnTime=\n"); + } + + val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1); + printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n", + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12), + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11), + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12), + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + { + scale = BITS(val, 29, 3); + if (scale > 5) + printf(" LTR1.2_Threshold="); + else + printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale)); + } + printf("\n"); + + val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2); + printf("\t\tL1SubCtl2:"); + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + { + time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5)); + if (time != -1) + printf(" T_PwrOn=%dus", time); + else + printf(" T_PwrOn="); + } + printf("\n"); +} + +static void +cap_ptm(struct device *d, int where) +{ + u32 buff; + u16 clock; + + printf("Precision Time Measurement\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + 4, 8)) + { + printf("\t\t\n"); + return; + } + + buff = get_conf_long(d, where + 4); + printf("\t\tPTMCap: "); + printf("Requester:%c Responder:%c Root:%c\n", + FLAG(buff, 0x1), + FLAG(buff, 0x2), + FLAG(buff, 0x4)); + + clock = BITS(buff, 8, 8); + printf("\t\tPTMClockGranularity: "); + switch (clock) + { + case 0x00: + printf("Unimplemented\n"); + break; + case 0xff: + printf("Greater than 254ns\n"); + break; + default: + printf("%huns\n", clock); + } + + buff = get_conf_long(d, where + 8); + printf("\t\tPTMControl: "); + printf("Enabled:%c RootSelected:%c\n", + FLAG(buff, 0x1), + FLAG(buff, 0x2)); + + clock = BITS(buff, 8, 8); + printf("\t\tPTMEffectiveGranularity: "); + switch (clock) + { + case 0x00: + printf("Unknown\n"); + break; + case 0xff: + printf("Greater than 254ns\n"); + break; + default: + printf("%huns\n", clock); + } +} + void -show_ext_caps(struct device *d) +show_ext_caps(struct device *d, int type) { int where = 0x100; char been_there[0x1000]; @@ -222,7 +717,7 @@ show_ext_caps(struct device *d) do { u32 header; - int id; + int id, version; if (!config_fetch(d, where, 4)) break; @@ -230,7 +725,11 @@ show_ext_caps(struct device *d) if (!header) break; id = header & 0xffff; - printf("\tCapabilities: [%03x] ", where); + version = (header >> 16) & 0xf; + printf("\tCapabilities: [%03x", where); + if (verbose > 1) + printf(" v%d", version); + printf("] "); if (been_there[where]++) { printf("\n"); @@ -238,11 +737,18 @@ show_ext_caps(struct device *d) } switch (id) { + case PCI_EXT_CAP_ID_NULL: + printf("Null\n"); + break; case PCI_EXT_CAP_ID_AER: - cap_aer(d, where); + cap_aer(d, where, type); + break; + case PCI_EXT_CAP_ID_DPC: + cap_dpc(d, where); break; case PCI_EXT_CAP_ID_VC: - printf("Virtual Channel \n"); + case PCI_EXT_CAP_ID_VC2: + cap_vc(d, where); break; case PCI_EXT_CAP_ID_DSN: cap_dsn(d, where); @@ -251,7 +757,7 @@ show_ext_caps(struct device *d) printf("Power Budgeting \n"); break; case PCI_EXT_CAP_ID_RCLINK: - printf("Root Complex Link \n"); + cap_rclink(d, where); break; case PCI_EXT_CAP_ID_RCILINK: printf("Root Complex Internal Link \n"); @@ -262,11 +768,11 @@ show_ext_caps(struct device *d) case PCI_EXT_CAP_ID_MFVC: printf("Multi-Function Virtual Channel \n"); break; - case PCI_EXT_CAP_ID_RBCB: - printf("Root Bridge Control Block \n"); + case PCI_EXT_CAP_ID_RCRB: + printf("Root Complex Register Block \n"); break; case PCI_EXT_CAP_ID_VNDR: - printf("Vendor Specific Information \n"); + cap_evendor(d, where); break; case PCI_EXT_CAP_ID_ACS: cap_acs(d, where); @@ -280,8 +786,74 @@ show_ext_caps(struct device *d) case PCI_EXT_CAP_ID_SRIOV: cap_sriov(d, where); break; + case PCI_EXT_CAP_ID_MRIOV: + printf("Multi-Root I/O Virtualization \n"); + break; + case PCI_EXT_CAP_ID_PRI: + cap_pri(d, where); + break; + case PCI_EXT_CAP_ID_REBAR: + printf("Resizable BAR \n"); + break; + case PCI_EXT_CAP_ID_DPA: + printf("Dynamic Power Allocation \n"); + break; + case PCI_EXT_CAP_ID_TPH: + cap_tph(d, where); + break; + case PCI_EXT_CAP_ID_LTR: + cap_ltr(d, where); + break; + case PCI_EXT_CAP_ID_SECPCI: + printf("Secondary PCI Express \n"); + break; + case PCI_EXT_CAP_ID_PMUX: + printf("Protocol Multiplexing \n"); + break; + case PCI_EXT_CAP_ID_PASID: + cap_pasid(d, where); + break; + case PCI_EXT_CAP_ID_LNR: + printf("LN Requester \n"); + break; + case PCI_EXT_CAP_ID_L1PM: + cap_l1pm(d, where); + break; + case PCI_EXT_CAP_ID_PTM: + cap_ptm(d, where); + break; + case PCI_EXT_CAP_ID_M_PCIE: + printf("PCI Express over M_PHY \n"); + break; + case PCI_EXT_CAP_ID_FRS: + printf("FRS Queueing \n"); + break; + case PCI_EXT_CAP_ID_RTR: + printf("Readiness Time Reporting \n"); + break; + case PCI_EXT_CAP_ID_DVSEC: + printf("Designated Vendor-Specific \n"); + break; + case PCI_EXT_CAP_ID_VF_REBAR: + printf("VF Resizable BAR \n"); + break; + case PCI_EXT_CAP_ID_DLNK: + printf("Data Link Feature \n"); + break; + case PCI_EXT_CAP_ID_16GT: + printf("Physical Layer 16.0 GT/s \n"); + break; + case PCI_EXT_CAP_ID_LMR: + printf("Lane Margining at the Receiver \n"); + break; + case PCI_EXT_CAP_ID_HIER_ID: + printf("Hierarchy ID \n"); + break; + case PCI_EXT_CAP_ID_NPEM: + printf("Native PCIe Enclosure Management \n"); + break; default: - printf("#%02x\n", id); + printf("Extended Capability ID %#02x\n", id); break; } where = (header >> 20) & ~3;