X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=5027e9a573fb6b7db4b749d94e1068a363f2caa6;hb=031254f2111f945ce6a1b8827e1a58ed7141fefe;hp=54f2336e9b8cc879816e97fd8cedc915040d10df;hpb=1c4f3780f7d939402cfe555007ebff45c8e38951;p=thirdparty%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 54f2336e9b8..5027e9a573f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,2155 +1,286 @@ -2018-10-05 Richard Henderson - - * or1k-asm.c: Regenerate. - -2018-10-03 Tamar Christina - - * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier. - * aarch64-dis.c (print_operands): Refactor to take notes. - (print_verifier_notes): New. - (print_aarch64_insn): Apply constraint verifier. - (print_insn_aarch64_word): Update call to print_aarch64_insn. - * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format. - -2018-10-03 Tamar Christina - - * aarch64-opc.c (init_insn_block): New. - (verify_constraints, aarch64_is_destructive_by_operands): New. - * aarch64-opc.h (verify_constraints): New. - -2018-10-03 Tamar Christina - - * aarch64-dis.c (aarch64_opcode_decode): Update verifier call. - * aarch64-opc.c (verify_ldpsw): Update arguments. - -2018-10-03 Tamar Christina - - * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove. - (aarch64_decode_insn, print_insn_aarch64_word): Use err_type. - -2018-10-03 Tamar Christina - - * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence. - * aarch64-dis.c (insn_sequence): New. - -2018-10-03 Tamar Christina - - * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN, - _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN, - _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN, - V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize - constraints. - (_SVE_INSNC): New. - (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize - constraints. - (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and - F_SCAN flags. - (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf, - sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech, - sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb, - sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd, - uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub, - uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add - C_SCAN_MOVPRFX and C_MAX_ELEM constraints. - -2018-10-02 Palmer Dabbelt - - * riscv-opc.c (riscv_opcodes) : New opcode. - -2018-09-23 Sandra Loosemore - - * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions - are used when extracting signed fields and converting them to - potentially 64-bit types. - -2018-09-21 Simon Marchi - - * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS. - * Makefile.in: Re-generate. - * aclocal.m4: Re-generate. - * configure: Re-generate. - * configure.ac: Remove check for -Wno-missing-field-initializers. - * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element. - (csky_v2_opcodes): Likewise. - -2018-09-20 Maciej W. Rozycki - - * arc-nps400-tbl.h: Append `ull' to large constants throughout. - -2018-09-20 Nelson Chu - - * nds32-asm.c (operand_fields): Remove the unused fields. - (nds32_opcodes): Remove the unused instructions. - * nds32-dis.c (nds32_ex9_info): Removed. - (nds32_parse_opcode): Updated. - (print_insn_nds32): Likewise. - * nds32-asm.c (config.h, stdlib.h, string.h): New includes. - (LEX_SET_FIELD, LEX_GET_FIELD): Update defines. - (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table, - build_opcode_hash_table): New functions. - (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table, - nds32_opcode_table): New. - (hw_ktabs): Declare it to a pointer rather than an array. - (build_hash_table): Removed. - * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT, - SYN_ROPT and upadte HW_GPR and HW_INT. - * nds32-dis.c (keywords): Remove const. - (match_field): New function. - (nds32_parse_opcode): Updated. - * disassemble.c (disassemble_init_for_target): - Add disassemble_init_nds32. - * nds32-dis.c (eum map_type): New. - (nds32_private_data): Likewise. - (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid, - nds32_add_opcode_hash_table, disassemble_init_nds32): New functions. - (print_insn_nds32): Updated. - * nds32-asm.c (parse_aext_reg): Add new parameter. - (parse_re, parse_re2, parse_aext_reg): Only reduced registers - are allowed to use. - All callers changed. - * nds32-asm.c (keyword_usr, keyword_sr): Updated. - (operand_fields): Add new fields. - (nds32_opcodes): Add new instructions. - (keyword_aridxi_mx): New keyword. - * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX - and NASM_ATTR_ZOL. - (ALU2_1, ALU2_2, ALU2_3): New macros. - * nds32-dis.c (nds32_filter_unknown_insn): Updated. - -2018-09-17 Kito Cheng - - * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu. - -2018-09-17 H.J. Lu - - PR gas/23670 - * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2, - EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2. - (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry. - (EVEX_LEN_0F7E_P_1): Likewise. - (EVEX_LEN_0F7E_P_2): Likewise. - (EVEX_LEN_0FD6_P_2): Likewise. - * i386-dis.c (USE_EVEX_LEN_TABLE): New. - (EVEX_LEN_TABLE): Likewise. - (EVEX_LEN_0F6E_P_2): New enum. - (EVEX_LEN_0F7E_P_1): Likewise. - (EVEX_LEN_0F7E_P_2): Likewise. - (EVEX_LEN_0FD6_P_2): Likewise. - (evex_len_table): New. - (get_valid_dis386): Handle USE_EVEX_LEN_TABLE. - * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq. - * i386-tbl.h: Regenerated. - -2018-09-17 H.J. Lu - - PR gas/23665 - * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and - VEX_LEN_0F7E_P_2 entries. - * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. - * i386-tbl.h: Regenerated. - -2018-09-17 H.J. Lu - - * i386-dis.c (VZERO_Fixup): Removed. - (VZERO): Likewise. - (VEX_LEN_0F10_P_1): Likewise. - (VEX_LEN_0F10_P_3): Likewise. - (VEX_LEN_0F11_P_1): Likewise. - (VEX_LEN_0F11_P_3): Likewise. - (VEX_LEN_0F2E_P_0): Likewise. - (VEX_LEN_0F2E_P_2): Likewise. - (VEX_LEN_0F2F_P_0): Likewise. - (VEX_LEN_0F2F_P_2): Likewise. - (VEX_LEN_0F51_P_1): Likewise. - (VEX_LEN_0F51_P_3): Likewise. - (VEX_LEN_0F52_P_1): Likewise. - (VEX_LEN_0F53_P_1): Likewise. - (VEX_LEN_0F58_P_1): Likewise. - (VEX_LEN_0F58_P_3): Likewise. - (VEX_LEN_0F59_P_1): Likewise. - (VEX_LEN_0F59_P_3): Likewise. - (VEX_LEN_0F5A_P_1): Likewise. - (VEX_LEN_0F5A_P_3): Likewise. - (VEX_LEN_0F5C_P_1): Likewise. - (VEX_LEN_0F5C_P_3): Likewise. - (VEX_LEN_0F5D_P_1): Likewise. - (VEX_LEN_0F5D_P_3): Likewise. - (VEX_LEN_0F5E_P_1): Likewise. - (VEX_LEN_0F5E_P_3): Likewise. - (VEX_LEN_0F5F_P_1): Likewise. - (VEX_LEN_0F5F_P_3): Likewise. - (VEX_LEN_0FC2_P_1): Likewise. - (VEX_LEN_0FC2_P_3): Likewise. - (VEX_LEN_0F3A0A_P_2): Likewise. - (VEX_LEN_0F3A0B_P_2): Likewise. - (VEX_W_0F10_P_0): Likewise. - (VEX_W_0F10_P_1): Likewise. - (VEX_W_0F10_P_2): Likewise. - (VEX_W_0F10_P_3): Likewise. - (VEX_W_0F11_P_0): Likewise. - (VEX_W_0F11_P_1): Likewise. - (VEX_W_0F11_P_2): Likewise. - (VEX_W_0F11_P_3): Likewise. - (VEX_W_0F12_P_0_M_0): Likewise. - (VEX_W_0F12_P_0_M_1): Likewise. - (VEX_W_0F12_P_1): Likewise. - (VEX_W_0F12_P_2): Likewise. - (VEX_W_0F12_P_3): Likewise. - (VEX_W_0F13_M_0): Likewise. - (VEX_W_0F14): Likewise. - (VEX_W_0F15): Likewise. - (VEX_W_0F16_P_0_M_0): Likewise. - (VEX_W_0F16_P_0_M_1): Likewise. - (VEX_W_0F16_P_1): Likewise. - (VEX_W_0F16_P_2): Likewise. - (VEX_W_0F17_M_0): Likewise. - (VEX_W_0F28): Likewise. - (VEX_W_0F29): Likewise. - (VEX_W_0F2B_M_0): Likewise. - (VEX_W_0F2E_P_0): Likewise. - (VEX_W_0F2E_P_2): Likewise. - (VEX_W_0F2F_P_0): Likewise. - (VEX_W_0F2F_P_2): Likewise. - (VEX_W_0F50_M_0): Likewise. - (VEX_W_0F51_P_0): Likewise. - (VEX_W_0F51_P_1): Likewise. - (VEX_W_0F51_P_2): Likewise. - (VEX_W_0F51_P_3): Likewise. - (VEX_W_0F52_P_0): Likewise. - (VEX_W_0F52_P_1): Likewise. - (VEX_W_0F53_P_0): Likewise. - (VEX_W_0F53_P_1): Likewise. - (VEX_W_0F58_P_0): Likewise. - (VEX_W_0F58_P_1): Likewise. - (VEX_W_0F58_P_2): Likewise. - (VEX_W_0F58_P_3): Likewise. - (VEX_W_0F59_P_0): Likewise. - (VEX_W_0F59_P_1): Likewise. - (VEX_W_0F59_P_2): Likewise. - (VEX_W_0F59_P_3): Likewise. - (VEX_W_0F5A_P_0): Likewise. - (VEX_W_0F5A_P_1): Likewise. - (VEX_W_0F5A_P_3): Likewise. - (VEX_W_0F5B_P_0): Likewise. - (VEX_W_0F5B_P_1): Likewise. - (VEX_W_0F5B_P_2): Likewise. - (VEX_W_0F5C_P_0): Likewise. - (VEX_W_0F5C_P_1): Likewise. - (VEX_W_0F5C_P_2): Likewise. - (VEX_W_0F5C_P_3): Likewise. - (VEX_W_0F5D_P_0): Likewise. - (VEX_W_0F5D_P_1): Likewise. - (VEX_W_0F5D_P_2): Likewise. - (VEX_W_0F5D_P_3): Likewise. - (VEX_W_0F5E_P_0): Likewise. - (VEX_W_0F5E_P_1): Likewise. - (VEX_W_0F5E_P_2): Likewise. - (VEX_W_0F5E_P_3): Likewise. - (VEX_W_0F5F_P_0): Likewise. - (VEX_W_0F5F_P_1): Likewise. - (VEX_W_0F5F_P_2): Likewise. - (VEX_W_0F5F_P_3): Likewise. - (VEX_W_0F60_P_2): Likewise. - (VEX_W_0F61_P_2): Likewise. - (VEX_W_0F62_P_2): Likewise. - (VEX_W_0F63_P_2): Likewise. - (VEX_W_0F64_P_2): Likewise. - (VEX_W_0F65_P_2): Likewise. - (VEX_W_0F66_P_2): Likewise. - (VEX_W_0F67_P_2): Likewise. - (VEX_W_0F68_P_2): Likewise. - (VEX_W_0F69_P_2): Likewise. - (VEX_W_0F6A_P_2): Likewise. - (VEX_W_0F6B_P_2): Likewise. - (VEX_W_0F6C_P_2): Likewise. - (VEX_W_0F6D_P_2): Likewise. - (VEX_W_0F6F_P_1): Likewise. - (VEX_W_0F6F_P_2): Likewise. - (VEX_W_0F70_P_1): Likewise. - (VEX_W_0F70_P_2): Likewise. - (VEX_W_0F70_P_3): Likewise. - (VEX_W_0F71_R_2_P_2): Likewise. - (VEX_W_0F71_R_4_P_2): Likewise. - (VEX_W_0F71_R_6_P_2): Likewise. - (VEX_W_0F72_R_2_P_2): Likewise. - (VEX_W_0F72_R_4_P_2): Likewise. - (VEX_W_0F72_R_6_P_2): Likewise. - (VEX_W_0F73_R_2_P_2): Likewise. - (VEX_W_0F73_R_3_P_2): Likewise. - (VEX_W_0F73_R_6_P_2): Likewise. - (VEX_W_0F73_R_7_P_2): Likewise. - (VEX_W_0F74_P_2): Likewise. - (VEX_W_0F75_P_2): Likewise. - (VEX_W_0F76_P_2): Likewise. - (VEX_W_0F77_P_0): Likewise. - (VEX_W_0F7C_P_2): Likewise. - (VEX_W_0F7C_P_3): Likewise. - (VEX_W_0F7D_P_2): Likewise. - (VEX_W_0F7D_P_3): Likewise. - (VEX_W_0F7E_P_1): Likewise. - (VEX_W_0F7F_P_1): Likewise. - (VEX_W_0F7F_P_2): Likewise. - (VEX_W_0FAE_R_2_M_0): Likewise. - (VEX_W_0FAE_R_3_M_0): Likewise. - (VEX_W_0FC2_P_0): Likewise. - (VEX_W_0FC2_P_1): Likewise. - (VEX_W_0FC2_P_2): Likewise. - (VEX_W_0FC2_P_3): Likewise. - (VEX_W_0FD0_P_2): Likewise. - (VEX_W_0FD0_P_3): Likewise. - (VEX_W_0FD1_P_2): Likewise. - (VEX_W_0FD2_P_2): Likewise. - (VEX_W_0FD3_P_2): Likewise. - (VEX_W_0FD4_P_2): Likewise. - (VEX_W_0FD5_P_2): Likewise. - (VEX_W_0FD6_P_2): Likewise. - (VEX_W_0FD7_P_2_M_1): Likewise. - (VEX_W_0FD8_P_2): Likewise. - (VEX_W_0FD9_P_2): Likewise. - (VEX_W_0FDA_P_2): Likewise. - (VEX_W_0FDB_P_2): Likewise. - (VEX_W_0FDC_P_2): Likewise. - (VEX_W_0FDD_P_2): Likewise. - (VEX_W_0FDE_P_2): Likewise. - (VEX_W_0FDF_P_2): Likewise. - (VEX_W_0FE0_P_2): Likewise. - (VEX_W_0FE1_P_2): Likewise. - (VEX_W_0FE2_P_2): Likewise. - (VEX_W_0FE3_P_2): Likewise. - (VEX_W_0FE4_P_2): Likewise. - (VEX_W_0FE5_P_2): Likewise. - (VEX_W_0FE6_P_1): Likewise. - (VEX_W_0FE6_P_2): Likewise. - (VEX_W_0FE6_P_3): Likewise. - (VEX_W_0FE7_P_2_M_0): Likewise. - (VEX_W_0FE8_P_2): Likewise. - (VEX_W_0FE9_P_2): Likewise. - (VEX_W_0FEA_P_2): Likewise. - (VEX_W_0FEB_P_2): Likewise. - (VEX_W_0FEC_P_2): Likewise. - (VEX_W_0FED_P_2): Likewise. - (VEX_W_0FEE_P_2): Likewise. - (VEX_W_0FEF_P_2): Likewise. - (VEX_W_0FF0_P_3_M_0): Likewise. - (VEX_W_0FF1_P_2): Likewise. - (VEX_W_0FF2_P_2): Likewise. - (VEX_W_0FF3_P_2): Likewise. - (VEX_W_0FF4_P_2): Likewise. - (VEX_W_0FF5_P_2): Likewise. - (VEX_W_0FF6_P_2): Likewise. - (VEX_W_0FF7_P_2): Likewise. - (VEX_W_0FF8_P_2): Likewise. - (VEX_W_0FF9_P_2): Likewise. - (VEX_W_0FFA_P_2): Likewise. - (VEX_W_0FFB_P_2): Likewise. - (VEX_W_0FFC_P_2): Likewise. - (VEX_W_0FFD_P_2): Likewise. - (VEX_W_0FFE_P_2): Likewise. - (VEX_W_0F3800_P_2): Likewise. - (VEX_W_0F3801_P_2): Likewise. - (VEX_W_0F3802_P_2): Likewise. - (VEX_W_0F3803_P_2): Likewise. - (VEX_W_0F3804_P_2): Likewise. - (VEX_W_0F3805_P_2): Likewise. - (VEX_W_0F3806_P_2): Likewise. - (VEX_W_0F3807_P_2): Likewise. - (VEX_W_0F3808_P_2): Likewise. - (VEX_W_0F3809_P_2): Likewise. - (VEX_W_0F380A_P_2): Likewise. - (VEX_W_0F380B_P_2): Likewise. - (VEX_W_0F3817_P_2): Likewise. - (VEX_W_0F381C_P_2): Likewise. - (VEX_W_0F381D_P_2): Likewise. - (VEX_W_0F381E_P_2): Likewise. - (VEX_W_0F3820_P_2): Likewise. - (VEX_W_0F3821_P_2): Likewise. - (VEX_W_0F3822_P_2): Likewise. - (VEX_W_0F3823_P_2): Likewise. - (VEX_W_0F3824_P_2): Likewise. - (VEX_W_0F3825_P_2): Likewise. - (VEX_W_0F3828_P_2): Likewise. - (VEX_W_0F3829_P_2): Likewise. - (VEX_W_0F382A_P_2_M_0): Likewise. - (VEX_W_0F382B_P_2): Likewise. - (VEX_W_0F3830_P_2): Likewise. - (VEX_W_0F3831_P_2): Likewise. - (VEX_W_0F3832_P_2): Likewise. - (VEX_W_0F3833_P_2): Likewise. - (VEX_W_0F3834_P_2): Likewise. - (VEX_W_0F3835_P_2): Likewise. - (VEX_W_0F3837_P_2): Likewise. - (VEX_W_0F3838_P_2): Likewise. - (VEX_W_0F3839_P_2): Likewise. - (VEX_W_0F383A_P_2): Likewise. - (VEX_W_0F383B_P_2): Likewise. - (VEX_W_0F383C_P_2): Likewise. - (VEX_W_0F383D_P_2): Likewise. - (VEX_W_0F383E_P_2): Likewise. - (VEX_W_0F383F_P_2): Likewise. - (VEX_W_0F3840_P_2): Likewise. - (VEX_W_0F3841_P_2): Likewise. - (VEX_W_0F38DB_P_2): Likewise. - (VEX_W_0F3A08_P_2): Likewise. - (VEX_W_0F3A09_P_2): Likewise. - (VEX_W_0F3A0A_P_2): Likewise. - (VEX_W_0F3A0B_P_2): Likewise. - (VEX_W_0F3A0C_P_2): Likewise. - (VEX_W_0F3A0D_P_2): Likewise. - (VEX_W_0F3A0E_P_2): Likewise. - (VEX_W_0F3A0F_P_2): Likewise. - (VEX_W_0F3A21_P_2): Likewise. - (VEX_W_0F3A40_P_2): Likewise. - (VEX_W_0F3A41_P_2): Likewise. - (VEX_W_0F3A42_P_2): Likewise. - (VEX_W_0F3A62_P_2): Likewise. - (VEX_W_0F3A63_P_2): Likewise. - (VEX_W_0F3ADF_P_2): Likewise. - (VEX_LEN_0F77_P_0): New. - (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11, - PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E, - PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52, - PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59, - PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C, - PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F, - PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62, - PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65, - PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68, - PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, - PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F, - PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4, - PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4, - PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2, - PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6, - PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75, - PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C, - PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2, - PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2, - PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5, - PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, - PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE, - PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1, - PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4, - PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8, - PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB, - PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE, - PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2, - PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5, - PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9, - PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC, - PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800, - PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803, - PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806, - PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809, - PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817, - PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E, - PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822, - PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825, - PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B, - PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832, - PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835, - PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839, - PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C, - PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F, - PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09, - PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C, - PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F, - PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries. - (vex_table): Update VEX 0F28 and 0F29 entries. - (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3, - VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0, - VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2, - VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1, - VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3, - VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1, - VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3, - VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1, - VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3, - VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and - VEX_LEN_0F3A0B_P_2 entries. - (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1, - VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1, - VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0, - VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2, - VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15, - VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1, - VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29, - VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0, - VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1, - VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1, - VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1, - VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1, - VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1, - VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2, - VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3, - VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3, - VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3, - VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3, - VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2, - VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2, - VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2, - VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2, - VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3, - VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2, - VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2, - VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2, - VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2, - VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3, - VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1, - VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0, - VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3, - VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2, - VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2, - VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2, - VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2, - VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2, - VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2, - VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3, - VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2, - VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2, - VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0, - VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2, - VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2, - VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2, - VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2, - VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2, - VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2, - VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2, - VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2, - VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2, - VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2, - VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2, - VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0, - VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2, - VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2, - VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2, - VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2, - VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2, - VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2, - VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2, - VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2, - VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2, - VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2, - VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and - VEX_W_0F3ADF_P_2 entries. - (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50, - MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2, - MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries. - -2018-09-17 H.J. Lu - - * i386-opc.tbl (VexWIG): New. - Replace VexW=3 with VexWIG. - -2018-09-15 H.J. Lu - - * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss. - * i386-tbl.h: Regenerated. - -2018-09-15 H.J. Lu - - PR gas/23665 - * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and - VEX_LEN_0FD6_P_2 entries. - * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq. - * i386-tbl.h: Regenerated. - -2018-09-14 H.J. Lu - - PR gas/23642 - * i386-opc.h (VEXWIG): New. - * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions. - * i386-tbl.h: Regenerated. - -2018-09-14 H.J. Lu - - PR binutils/23655 - * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for - vcvtsi2sd%LQ and vcvtusi2sd%LQ. - * i386-dis.c (EXxEVexR64): New. - (evex_rounding_64_mode): Likewise. - (OP_Rounding): Handle evex_rounding_64_mode. - -2018-09-14 H.J. Lu - - PR binutils/23655 - * i386-dis-evex.h (evex_table): Replace Eq with Edqa for - vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ. - * i386-dis.c (Edqa): New. - (dqa_mode): Likewise. - (intel_operand_size): Handle dqa_mode as m_mode. - (OP_E_register): Handle dqa_mode as dq_mode. - (OP_E_memory): Set shift for dqa_mode based on address_mode. - -2018-09-14 H.J. Lu - - * i386-dis.c (OP_E_memory): Reformat. - -2018-09-14 Jan Beulich - - * i386-opc.tbl (crc32): Fold byte and word forms. - * i386-tbl.h: Re-generate. - -2018-09-13 H.J. Lu - - * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd, - pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd. - Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and - vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq. - * i386-tbl.h: Regenerated. - -2018-09-13 Jan Beulich - - * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where - meaningless. - (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors, - xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq, - rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and - AVX512_4VNNIW insns. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where - meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where - meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where - meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where - meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where - meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from SHA insns. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where - meaningless. - * i386-tbl.h: Re-generate. +2019-04-15 Thomas Preud'homme -2018-09-13 Jan Beulich + * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. - * i386-opc.tbl: Drop IgnoreSize from AVX insns where - meaningless. - * i386-tbl.h: Re-generate. +2019-04-12 John Darrington -2018-09-13 Jan Beulich + s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with + "optr". ("operator" is a reserved word in c++). - * i386-opc.tbl: Drop IgnoreSize from GNFI insns. - * i386-tbl.h: Re-generate. +2019-04-11 Sudakshina Das -2018-09-13 Jan Beulich + * aarch64-opc.c (aarch64_print_operand): Add case for + AARCH64_OPND_Rt_SP. + (verify_constraints): Likewise. + * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. + (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions + to accept Rt|SP as first operand. + (AARCH64_OPERANDS): Add new Rt_SP. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. - * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns. - * i386-tbl.h: Re-generate. +2019-04-11 Sudakshina Das -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where - meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where - meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where - meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64. - (vpbroadcastw, rdpid): Drop NoRex64. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl (vmovsd, vmovss): Fold register form load and - store templates, adding D. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd, - movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps, - movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd, - vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32, - vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups): - Fold load and store templates where possible, adding D. Drop - IgnoreSize where it was pointlessly present. Drop redundant - *word. - * i386-tbl.h: Re-generate. - -2018-09-13 Jan Beulich - - * i386-dis.c (Mv_bnd, v_bndmk_mode): New. - (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk. - (intel_operand_size): Handle v_bndmk_mode. - (OP_E_memory): Likewise. Produce (bad) when also riprel. - -2018-09-08 John Darrington - - * disassemble.c (ARCH_s12z): Define if ARCH_all. - -2018-08-31 Kito Cheng - - * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for - compressed floating point instructions. - -2018-08-30 Kito Cheng - - * riscv-dis.c (riscv_disassemble_insn): Check XLEN by - riscv_opcode.xlen_requirement. - * riscv-opc.c (riscv_opcodes): Update for struct change. - -2018-08-29 Martin Aberg - - * sparc-opc.c (sparc_opcodes): Add Leon specific partial write - psr (PWRPSR) instruction. - -2018-08-29 Chenghua Xu - - * mips-dis.c (mips_arch_choices): Add gs264e descriptors. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. + * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. -2018-08-29 Chenghua Xu +2019-04-09 Robert Suchanek - * mips-dis.c (mips_arch_choices): Add gs464e descriptors. + * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. -2018-08-29 Chenghua Xu +2019-04-08 H.J. Lu - * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep - loongson3a as an alias of gs464 for compatibility. - * mips-opc.c (mips_opcodes): Change Comments. + * i386-opc.tbl: Consolidate AVX512 BF16 entries. + * i386-init.h: Regenerated. -2018-08-29 Chenghua Xu +2019-04-07 Alan Modra - * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext - option. - (print_mips_disassembler_options): Document -M loongson-ext. - * mips-opc.c (LEXT2): New macro. - (mips_opcodes): Add cto, ctz, dcto, dctz instructions. + * ppc-dis.c (print_insn_powerpc): Use a tiny state machine + op_separator to control printing of spaces, comma and parens + rather than need_comma, need_paren and spaces vars. -2018-08-29 Chenghua Xu +2019-04-07 Alan Modra - * mips-dis.c (mips_arch_choices): Add EXT to loongson3a - descriptors. - (parse_mips_ase_option): Handle -M loongson-ext option. - (print_mips_disassembler_options): Document -M loongson-ext. - * mips-opc.c (IL3A): Delete. - * mips-opc.c (LEXT): New macro. - (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT - instructions. + PR 24421 + * arm-dis.c (print_insn_coprocessor): Correct bracket placement. + (print_insn_neon, print_insn_arm): Likewise. -2018-08-29 Chenghua Xu +2019-04-05 Xuepeng Guo - * mips-dis.c (mips_arch_choices): Add CAM to loongson3a - descriptors. - (parse_mips_ase_option): Handle -M loongson-cam option. - (print_mips_disassembler_options): Document -M loongson-cam. - * mips-opc.c (LCAM): New macro. - (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM + * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. - -2018-08-21 Alan Modra - - * ppc-dis.c (operand_value_powerpc): Init "invalid". - (skip_optional_operands): Count optional operands, and update - ppc_optional_operand_value call. - * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg. - (extract_vlensi): Likewise. - (extract_fxm): Return default value for missing optional operand. - (extract_ls, extract_raq, extract_tbr): Likewise. - (insert_sxl, extract_sxl): New functions. - (insert_esync, extract_esync): Remove Power9 handling and simplify. - (powerpc_operands ): Delete PPC_OPERAND_OPTIONAL_VALUE - flag and extra entry. - (powerpc_operands ): Likewise, and use insert_sxl and - extract_sxl. - -2018-08-20 Alan Modra - - * sh-opc.h (MASK): Simplify. - -2018-08-18 John Darrington - - * s12z-dis.c (bm_decode): Deal with cases where the mode is - BM_RESERVED0 or BM_RESERVED1 - (bm_rel_decode, bm_n_bytes): Ditto. - -2018-08-18 John Darrington - - * s12z.h: Delete. - -2018-08-14 H.J. Lu - - * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for - address with the addr32 prefix and without base nor index - registers. - -2018-08-11 H.J. Lu - - * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to - CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS, - CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS. - (cpu_flags): Add CpuCMOV and CpuFXSR. - * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64, - fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC. + * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 + and EVEX_W_0F3872_P_3. + * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. + (cpu_flags): Add bitfield for CpuAVX512_BF16. + * i386-opc.h (enum): Add CpuAVX512_BF16. + (i386_cpu_flags): Add bitfield for cpuavx512_bf16. + * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. -2018-08-06 Claudiu Zissulescu - - * arc-regs.h: Update auxiliary registers. - -2018-08-06 Jan Beulich - - * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines. - (RegIP, RegIZ): Define. - * i386-reg.tbl: Adjust comments. - (rip): Use Qword instead of BaseIndex. Use RegIP. - (eip): Use Dword instead of BaseIndex. Use RegIP. - (riz): Add Qword. Use RegIZ. - (eiz): Add Dword. Use RegIZ. - * i386-tbl.h: Re-generate. - -2018-08-03 Jan Beulich - - * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw, - pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw, - vpmovzxdq, vpmovzxwd): Remove NoRex64. - * i386-tbl.h: Re-generate. - -2018-08-03 Jan Beulich - - * i386-gen.c (operand_types): Remove Mem field. - * i386-opc.h (union i386_operand_type): Remove mem field. - * i386-init.h, i386-tbl.h: Re-generate. - -2018-08-01 Alan Modra - - * po/POTFILES.in: Regenerate. - -2018-07-31 Nick Clifton - - * po/sv.po: Updated Swedish translation. - -2018-07-31 Jan Beulich - - * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize. - * i386-init.h, i386-tbl.h: Re-generate. - -2018-07-31 Jan Beulich - - * i386-opc.h (ZEROING_MASKING) Rename to ... - (DYNAMIC_MASKING): ... this. Adjust comment. - * i386-opc.tbl (MaskingMorZ): Define. - (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4, - vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4, - vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps, - vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64, - vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd, - vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw, - vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb, - vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw, - vpmovuswb, vpmovwb): Fold AVX512 register and memory forms. - -2018-07-31 Jan Beulich - - * i386-opc.tbl: Use element rather than vector size for AVX512* - scatter/gather insns. - * i386-tbl.h: Re-generate. - -2018-07-31 Jan Beulich - - * i386-gen.c (cpu_flag_init): Drop CpuVREX uses. - (cpu_flags): Drop CpuVREX. - * i386-opc.h (CpuVREX): Delete. - (union i386_cpu_flags): Remove cpuvrex. - * i386-init.h, i386-tbl.h: Re-generate. - -2018-07-30 Jim Wilson - - * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size - fields. - * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns. - -2018-07-30 Andrew Jenner - - * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. - * Makefile.in: Regenerated. - * configure.ac: Add C-SKY. - * configure: Regenerated. - * csky-dis.c: New file. - * csky-opc.h: New file. - * disassemble.c (ARCH_csky): Define. - (disassembler, disassemble_init_for_target): Add case for ARCH_csky. - * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. - -2018-07-27 Alan Modra - - * ppc-opc.c (insert_sprbat): Correct function parameter and - return type. - (extract_sprbat): Likewise, variable too. - -2018-07-26 Alex Chadwick - Alan Modra - - * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. - (powerpc_init_dialect): Handle bfd_mach_ppc_750. - * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to - support disjointed BAT. - (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. - (XSPRGQR_MASK, GEKKO, BROADWAY): Define. - (powerpc_opcodes): Add 750cl extended mnemonics for spr access. - -2018-07-25 H.J. Lu - Igor Tsimbalist - - * i386-gen.c (adjust_broadcast_modifier): New function. - (process_i386_opcode_modifier): Add an argument for operands. - Adjust the Broadcast value based on operands. - (output_i386_opcode): Pass operand_types to - process_i386_opcode_modifier. - (process_i386_opcodes): Pass NULL as operands to - process_i386_opcode_modifier. - * i386-opc.h (BYTE_BROADCAST): New. - (WORD_BROADCAST): Likewise. - (DWORD_BROADCAST): Likewise. - (QWORD_BROADCAST): Likewise. - (i386_opcode_modifier): Expand broadcast to 3 bits. - * i386-tbl.h: Regenerated. - -2018-07-24 Alan Modra - - PR 23430 - * or1k-desc.h: Regenerate. - -2018-07-24 Jan Beulich - - * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd, - vcvtusi2ss, and vcvtusi2sd. - * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss): - Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms. - * i386-tbl.h: Re-generate. - -2018-07-23 Claudiu Zissulescu - - * arc-opc.c (extract_w6): Fix extending the sign. - -2018-07-23 Claudiu Zissulescu - - * arc-tbl.h (vewt): Allow it for ARC EM family. - -2018-07-23 Alan Modra - - PR 23419 - * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended - opcode variants for mtspr/mfspr encodings. - -2018-07-20 Chenghua Xu - Maciej W. Rozycki +2019-04-05 Alan Modra + + * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. + (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics + to favour printing of "-" branch hint when using the "y" bit. + Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. + +2019-04-05 Alan Modra + + * ppc-dis.c (print_insn_powerpc): Delay printing spaces after + opcode until first operand is output. + +2019-04-04 Peter Bergner + + PR gas/24349 + * ppc-opc.c (valid_bo_pre_v2): Add comments. + (valid_bo_post_v2): Add support for 'at' branch hints. + (insert_bo): Only error on branch on ctr. + (get_bo_hint_mask): New function. + (insert_boe): Add new 'branch_taken' formal argument. Add support + for inserting 'at' branch hints. + (extract_boe): Add new 'branch_taken' formal argument. Add support + for extracting 'at' branch hints. + (insert_bom, extract_bom, insert_bop, extract_bop): New functions. + (BOE): Delete operand. + (BOM, BOP): New operands. + (RM): Update value. + (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. + (powerpc_opcodes) : Replace BOE with BOM. + (powerpc_opcodes) : Replace BOE with BOP. + : New extended mnemonics. + +2019-03-28 Alan Modra + + PR 24390 + * ppc-opc.c (BTF): Define. + (powerpc_opcodes): Use for mtfsb*. + * ppc-dis.c (print_insn_powerpc): Print fields with both + PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. + +2019-03-25 Tamar Christina + + * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. + (mapping_symbol_for_insn): Implement new algorithm. + (print_insn): Remove duplicate code. + +2019-03-25 Tamar Christina + + * aarch64-dis.c (print_insn_aarch64): + Implement override. + +2019-03-25 Tamar Christina + + * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search + order. + +2019-03-25 Tamar Christina + + * aarch64-dis.c (last_stop_offset): New. + (print_insn_aarch64): Use stop_offset. + +2019-03-19 H.J. Lu + + PR gas/24359 + * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to + CPU_ANY_AVX2_FLAGS. + * i386-init.h: Regenerated. - * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and - loongson3a descriptors. - (parse_mips_ase_option): Handle -M loongson-mmi option. - (print_mips_disassembler_options): Document -M loongson-mmi. - * mips-opc.c (LMMI): New macro. - (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI - instructions. +2019-03-18 H.J. Lu -2018-07-19 Jan Beulich - - * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, - vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop - IgnoreSize and [XYZ]MMword where applicable. - * i386-tbl.h: Re-generate. - -2018-07-19 Jan Beulich - - * i386-opc.tbl (vfpclasspd, vfpclassps): Fold. - (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord. - (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord. - (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord. - * i386-tbl.h: Re-generate. - -2018-07-19 Jan Beulich - - * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ, - AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and - VPCLMULQDQ templates into their respective AVX512VL counterparts - where possible, using Disp8ShiftVL and CheckRegSize instead of - Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate. - * i386-tbl.h: Re-generate. - -2018-07-19 Jan Beulich - - * i386-opc.tbl: Fold AVX512DQ templates into their respective - AVX512VL counterparts where possible, using Disp8ShiftVL and - CheckRegSize instead of Evex= plus Disp8MemShift= (plus often - IgnoreSize) as appropriate. - * i386-tbl.h: Re-generate. - -2018-07-19 Jan Beulich - - * i386-opc.tbl: Fold AVX512BW templates into their respective - AVX512VL counterparts where possible, using Disp8ShiftVL and - CheckRegSize instead of Evex= plus Disp8MemShift= (plus often - IgnoreSize) as appropriate. - * i386-tbl.h: Re-generate. - -2018-07-19 Jan Beulich - - * i386-opc.tbl: Fold AVX512CD templates into their respective - AVX512VL counterparts where possible, using Disp8ShiftVL and - CheckRegSize instead of Evex= plus Disp8MemShift= (plus often - IgnoreSize) as appropriate. - * i386-tbl.h: Re-generate. - -2018-07-19 Jan Beulich - - * i386-opc.h (DISP8_SHIFT_VL): New. - * i386-opc.tbl (Disp8ShiftVL): Define. - (various): Fold AVX512VL templates into their respective - AVX512F counterparts where possible, using Disp8ShiftVL and - CheckRegSize instead of Evex= plus Disp8MemShift= (plus often - IgnoreSize) as appropriate. - * i386-tbl.h: Re-generate. - -2018-07-19 Jan Beulich - - * Makefile.am: Change dependencies and rule for - $(srcdir)/i386-init.h. - * Makefile.in: Re-generate. - * i386-gen.c (process_i386_opcodes): New local variable - "marker". Drop opening of input file. Recognize marker and line - number directives. - * i386-opc.tbl (OPCODE_I386_H): Define. - (i386-opc.h): Include it. - (None): Undefine. - -2018-07-18 H.J. Lu - - PR gas/23418 - * i386-opc.h (Byte): Update comments. - (Word): Likewise. - (Dword): Likewise. - (Fword): Likewise. - (Qword): Likewise. - (Tbyte): Likewise. - (Xmmword): Likewise. - (Ymmword): Likewise. - (Zmmword): Likewise. - * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and - vcvttps2uqq. + PR gas/24348 + * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, + vmovdqu16, vmovdqu32 and vmovdqu64. * i386-tbl.h: Regenerated. -2018-07-12 Sudakshina Das - - * aarch64-tbl.h (aarch64_opcode_table): Add entry for - ssbb and pssbb and update dsb flags to F_HAS_ALIAS. - * aarch64-asm-2.c: Regenerate. - * aarch64-dis-2.c: Regenerate. - * aarch64-opc-2.c: Regenerate. - -2018-07-12 Tamar Christina +2019-03-12 Andreas Krebbel - PR binutils/23192 - * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, - mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, - umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, - sqdmulh, sqrdmulh): Use Em16. + * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand + from vstrszb, vstrszh, and vstrszf. -2018-07-11 Sudakshina Das +2019-03-12 Andreas Krebbel - * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move - csdb together with them. - (thumb32_opcodes): Likewise. + * s390-opc.txt: Add instruction descriptions. -2018-07-11 Jan Beulich +2019-02-08 Jim Wilson - * i386-opc.tbl (monitor, monitorx): Add 64-bit template - requiring 32-bit registers as operands 2 and 3. Improve - comments. - (mwait, mwaitx): Fold templates. Improve comments. - OPERAND_TYPE_INOUTPORTREG. - * i386-tbl.h: Re-generate. + * riscv-opc.c (riscv_opcodes) : Use Cz to compress 3 operand form. + : Likewise. -2018-07-11 Jan Beulich +2019-02-07 Tamar Christina - * i386-gen.c (operand_type_init): Remove - OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of - OPERAND_TYPE_INOUTPORTREG. - * i386-init.h: Re-generate. + * arm-dis.c (arm_opcodes): Redefine hlt to armv1. -2018-07-11 Jan Beulich +2019-02-07 Tamar Christina - * i386-opc.tbl (wrssd, wrussd): Add Dword. - (wrssq, wrussq): Add Qword. - * i386-tbl.h: Re-generate. + PR binutils/23212 + * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. + * aarch64-opc.c (verify_elem_sd): New. + (fields): Add FLD_sz entr. + * aarch64-tbl.h (_SIMD_INSN): New. + (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and + fmulx scalar and vector by element isns. -2018-07-11 Jan Beulich +2019-02-07 Nick Clifton - * i386-opc.h: Rename OTMax to OTNum. - (OTNumOfUints): Adjust calculation. - (OTUnused): Directly alias to OTNum. - -2018-07-09 Maciej W. Rozycki - - * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to - `reg_xys'. - (lea_reg_xys): Likewise. - (print_insn_loop_primitive): Rename `reg' local variable to - `reg_dxy'. - -2018-07-06 Tamar Christina - - PR binutils/23242 - * aarch64-tbl.h (ldarh): Fix disassembly mask. - -2018-07-06 Tamar Christina - - PR binutils/23369 - * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, - vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. + * po/sv.po: Updated Swedish translation. -2018-07-02 Maciej W. Rozycki +2019-01-31 Andreas Krebbel - PR tdep/8282 - * mips-dis.c (mips_option_arg_t): New enumeration. - (mips_options): New variable. - (disassembler_options_mips): New function. - (print_mips_disassembler_options): Reimplement in terms of - `disassembler_options_mips'. - * arm-dis.c (disassembler_options_arm): Adapt to using the - `disasm_options_and_args_t' structure. - * ppc-dis.c (disassembler_options_powerpc): Likewise. - * s390-dis.c (disassembler_options_s390): Likewise. + * s390-mkopc.c (main): Accept arch13 as cpu string. + * s390-opc.c: Add new instruction formats and instruction opcode + masks. + * s390-opc.txt: Add new arch13 instructions. -2018-07-02 Thomas Preud'homme +2019-01-25 Sudakshina Das - * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in - expected result. - * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. - * testsuite/ld-arm/tls-longplt-lib.d: Likewise. - * testsuite/ld-arm/tls-longplt.d: Likewise. + * aarch64-tbl.h (QL_LDST_AT): Update macro. + (aarch64_opcode): Change encoding for stg, stzg + st2g and st2zg. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. -2018-06-29 Tamar Christina +2019-01-25 Sudakshina Das - PR binutils/23192 - * aarch64-asm-2.c: Regenerate. + * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. - * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. - * aarch64-opc.c (operand_general_constraint_met_p, - aarch64_print_operand): Likewise. - * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, - smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, - fmlal2, fmlsl2. - (AARCH64_OPERANDS): Add Em2. - -2018-06-26 Nick Clifton + * aarch64-tbl.h (aarch64_opcode): Add new stzgm. + +2019-01-25 Sudakshina Das + Ramana Radhakrishnan + + * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. + * aarch64-asm.h (ins_addr_simple_2): Likeiwse. + * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. + * aarch64-dis.h (ext_addr_simple_2): Likewise. + * aarch64-opc.c (operand_general_constraint_met_p): Remove + case for ldstgv_indexed. + (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. + * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. + (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2019-01-23 Nick Clifton - * po/uk.po: Updated Ukranian translation. - * po/de.po: Updated German translation. * po/pt_BR.po: Updated Brazilian Portuguese translation. -2018-06-26 Nick Clifton +2019-01-21 Nick Clifton - * nfp-dis.c: Fix spelling mistake. + * po/de.po: Updated German translation. + * po/uk.po: Updated Ukranian translation. -2018-06-24 Nick Clifton +2019-01-20 Chenghua Xu + * mips-dis.c (mips_arch_choices): Fix typo in + gs464, gs464e and gs264e descriptors. + +2019-01-19 Nick Clifton * configure: Regenerate. * po/opcodes.pot: Regenerate. 2018-06-24 Nick Clifton - 2.31 branch created. - -2018-06-19 Tamar Christina - - * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs - * aarch64-asm-2.c: Regenerate. - * aarch64-dis-2.c: Likewise. - -2018-06-21 Maciej W. Rozycki - - * mips-dis.c (print_mips_disassembler_options): Fix a typo in - `-M ginv' option description. - -2018-06-20 Sebastian Huber - - PR gas/23305 - * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for - la and lla. - -2018-06-19 Simon Marchi - - * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11. - * configure.ac: Remove AC_PREREQ. - * Makefile.in: Re-generate. - * aclocal.m4: Re-generate. - * configure: Re-generate. - -2018-06-14 Faraz Shahbazker - - * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and - mips64r6 descriptors. - (parse_mips_ase_option): Handle -Mginv option. - (print_mips_disassembler_options): Document -Mginv. - * mips-opc.c (decode_mips_operand) <+\>: New operand format. - (GINV): New macro. - (mips_opcodes): Define ginvi and ginvt. - -2018-06-13 Scott Egerton - Faraz Shahbazker - - * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs. - * mips-opc.c (CRC, CRC64): New macros. - (mips_builtin_opcodes): Define crc32b, crc32h, crc32w, - crc32cb, crc32ch and crc32cw for CRC. Define crc32d and - crc32cd for CRC64. - -2018-06-08 Egeyar Bagcioglu - - PR 20319 - * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV. - (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV. - -2018-06-06 Alan Modra - - * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after - setjmp. Move init for some other vars later too. + 2.32 branch created. -2018-06-04 Max Filippov +2019-01-09 John Darrington - * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes. - (dis_private): Add new fields for property section tracking. - (xtensa_coalesce_insn_tables, xtensa_find_table_entry) - (xtensa_instruction_fits): New functions. - (fetch_data): Bump minimal fetch size to 4. - (print_insn_xtensa): Make struct dis_private static. - Load and prepare property table on section change. - Don't disassemble literals. Don't disassemble instructions that - cross property table boundaries. + * s12z-dis.c (print_insn_s12z): Do not dereference an operand + if it is null. + -dis.c (opr_emit_disassembly): Do not omit an index if it is + zero. -2018-06-01 H.J. Lu +2019-01-09 Andrew Paprocki - * configure: Regenerated. - -2018-06-01 Jan Beulich - - * i386-opc.tbl (mov, movq): Fold to/from SReg* forms. - * i386-tbl.h: Re-generate. - -2018-06-01 Jan Beulich - - * i386-opc.tbl (sldt, str): Add NoRex64. - * i386-tbl.h: Re-generate. - -2018-06-01 Jan Beulich - - * i386-opc.tbl (invpcid): Add Oword. - * i386-tbl.h: Re-generate. - -2018-06-01 Alan Modra - - * sysdep.h (_bfd_error_handler): Don't declare. - * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here. - * rl78-decode.opc: Likewise. - * msp430-decode.c: Regenerate. - * rl78-decode.c: Regenerate. - -2018-05-30 Amit Pawar - - * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS. - * i386-init.h : Regenerated. - -2018-05-25 Alan Modra - - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - -2018-05-21 Peter Bergner - - * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba, - insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions. - (insert_bab, extract_bab, insert_btab, extract_btab, - insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions. - (BAT, BBA VBA RBS XB6S): Delete macros. - (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros. - (BB, BD, RBX, XC6): Update for new macros. - (powerpc_opcodes) : Likewise. - * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands. - -2018-05-18 John Darrington - - * Makefile.am: Add support for s12z architecture. - * configure.ac: Likewise. - * disassemble.c: Likewise. - * disassemble.h: Likewise. - * Makefile.in: Regenerate. * configure: Regenerate. - * s12z-dis.c: New file. - * s12z.h: New file. - -2018-05-18 Alan Modra - - * nfp-dis.c: Don't #include libbfd.h. - (init_nfp3200_priv): Use bfd_get_section_contents. - (nit_nfp6000_mecsr_sec): Likewise. - -2018-05-17 Nick Clifton - - * po/zh_CN.po: Updated simplified Chinese translation. - -2018-05-16 Tamar Christina - - PR binutils/23109 - * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot. - * aarch64-dis-2.c: Regenerate. - -2018-05-15 Tamar Christina - - PR binutils/21446 - * aarch64-asm.c (opintl.h): Include. - (aarch64_ins_sysreg): Enforce read/write constraints. - * aarch64-dis.c (aarch64_ext_sysreg): Likewise. - * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here. - (F_REG_READ, F_REG_WRITE): New. - * aarch64-opc.c (aarch64_print_operand): Generate notes for - AARCH64_OPND_SYSREG. - (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h. - (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0, - mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1, - id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1, - id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1, - id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1, - mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1, - id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1, - id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1, - id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1, - csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2, - rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0, - mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1, - mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1, - pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0. - * aarch64-tbl.h (aarch64_opcode_table): Add constraints to - msr (F_SYS_WRITE), mrs (F_SYS_READ). - -2018-05-15 Tamar Christina - - PR binutils/21446 - * aarch64-dis.c (no_notes: New. - (parse_aarch64_dis_option): Support notes. - (aarch64_decode_insn, print_operands): Likewise. - (print_aarch64_disassembler_options): Document notes. - * aarch64-opc.c (aarch64_print_operand): Support notes. - -2018-05-15 Tamar Christina - - PR binutils/21446 - * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean - and take error struct. - * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, - aarch64_ins_reglist, aarch64_ins_ldst_reglist, - aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, - aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, - aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, - aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, - aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, - aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, - aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, - aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, - aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, - aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, - aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, - aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, - aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, - aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, - aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, - aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, - aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, - aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, - aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, - aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, - aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, - aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, - aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. - * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. - * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, - aarch64_ext_reglist, aarch64_ext_ldst_reglist, - aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, - aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, - aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, - aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, - aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, - aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, - aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, - aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, - aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, - aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, - aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, - aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, - aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, - aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, - aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, - aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, - aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, - aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, - aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, - aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, - aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, - aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, - aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. - (determine_disassembling_preference, aarch64_decode_insn, - print_insn_aarch64_word, print_insn_data): Take errors struct. - (print_insn_aarch64): Use errors. - * aarch64-asm-2.c: Regenerate. - * aarch64-dis-2.c: Regenerate. - * aarch64-gen.c (print_operand_inserter): Use errors and change type to - boolean in aarch64_insert_operan. - (print_operand_extractor): Likewise. - * aarch64-opc.c (aarch64_print_operand): Use sysreg struct. - -2018-05-15 Francois H. Theron - - * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma. - -2018-05-09 H.J. Lu - - * i386-opc.tbl: Remove Disp from movidir{i,64b}. - -2018-05-09 Sebastian Rasmussen - - * cr16-opc.c (cr16_instruction): Comment typo fix. - * hppa-dis.c (print_insn_hppa): Likewise. - -2018-05-08 Jim Wilson - - * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. - (match_c_slli64, match_srxi_as_c_srxi): New. - (riscv_opcodes) : Use match_slli_as_c_slli. - : Use match_srxi_as_c_srxi. - : Use match_s_slli. - : New. - -2018-05-08 Alan Modra - - * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP. - (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to - partition opcode space for index lookup. - -2018-05-07 Peter Bergner - - * ppc-dis.c (print_insn_powerpc) : Replace this... - : ...with this. Update usage. - Remove duplicate call to *info->memory_error_func. - -2018-05-07 Igor Tsimbalist - H.J. Lu - - * i386-dis.c (Gva): New. - (enum): Add PREFIX_0F38F8, PREFIX_0F38F9, - MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0. - (prefix_table): New instructions (see prefix above). - (mod_table): New instructions (see prefix above). - (OP_G): Handle va_mode. - * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, - CPU_MOVDIR64B_FLAGS. - (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B. - * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. - (i386_cpu_flags): Add cpumovdiri and cpumovdir64b. - * i386-opc.tbl: Add movidir{i,64b}. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. -2018-05-07 H.J. Lu +2019-01-07 Alan Modra - * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with - AddrPrefixOpReg. - * i386-opc.h (AddrPrefixOp0): Renamed to ... - (AddrPrefixOpReg): This. - (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg. - * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg. - -2018-05-07 Peter Bergner - - * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned. - (vle_num_opcodes): Likewise. - (spe2_num_opcodes): Likewise. - * ppc-dis.c (disassemble_init_powerpc) : Rewrite - initialization loop. - (disassemble_init_powerpc) : Likewise. - (disassemble_init_powerpc) : Likewise. Initialize - only once. - -2018-05-01 Tamar Christina - - * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code. - -2018-04-30 Francois H. Theron - - Makefile.am: Added nfp-dis.c. - configure.ac: Added bfd_nfp_arch. - disassemble.h: Added print_insn_nfp prototype. - disassemble.c: Added ARCH_nfp and call to print_insn_nfp - nfp-dis.c: New, for NFP support. - po/POTFILES.in: Added nfp-dis.c to the list. - Makefile.in: Regenerate. - configure: Regenerate. - -2018-04-26 Jan Beulich - - * i386-opc.tbl: Fold various non-memory operand AVX512VL - templates into their base ones. - * i386-tlb.h: Re-generate. - -2018-04-26 Jan Beulich - - * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for - CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use - CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to - CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS. - * i386-init.h: Re-generate. - -2018-04-26 Jan Beulich - - * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX, - CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use - CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment. - Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus - comment. - (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM, - and CpuRegMask. - * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM, - CpuRegMask: Delete. - (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm, - cpuregzmm, and cpuregmask. - * i386-init.h: Re-generate. - * i386-tbl.h: Re-generate. - -2018-04-26 Jan Beulich - - * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only. - CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only. - * i386-init.h: Re-generate. - -2018-04-26 Jan Beulich - - * i386-gen.c (VexImmExt): Delete. - * i386-opc.h (VexImmExt, veximmext): Delete. - * i386-opc.tbl: Drop all VexImmExt uses. - * i386-tlb.h: Re-generate. - -2018-04-25 Jan Beulich - - * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL - register-only forms. - * i386-tlb.h: Re-generate. - -2018-04-25 Tamar Christina - - * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks. - -2018-04-17 Igor Tsimbalist - - * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0, - PREFIX_0F1C. - * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS, - (cpu_flags): Add CpuCLDEMOTE. - * i386-init.h: Regenerate. - * i386-opc.h (enum): Add CpuCLDEMOTE, - (i386_cpu_flags): Add cpucldemote. - * i386-opc.tbl: Add cldemote. - * i386-tbl.h: Regenerate. - -2018-04-16 Alan Modra - - * Makefile.am: Remove sh5 and sh64 support. - * configure.ac: Likewise. - * disassemble.c: Likewise. - * disassemble.h: Likewise. - * sh-dis.c: Likewise. - * sh64-dis.c: Delete. - * sh64-opc.c: Delete. - * sh64-opc.h: Delete. - * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. -2018-04-16 Alan Modra +2019-01-03 John Darrington - * Makefile.am: Remove w65 support. - * configure.ac: Likewise. - * disassemble.c: Likewise. - * disassemble.h: Likewise. - * w65-dis.c: Delete. - * w65-opc.h: Delete. + * s12z-opc.c: New file. + * s12z-opc.h: New file. + * s12z-dis.c: Removed all code not directly related to display + of instructions. Used the interface provided by the new files + instead. + * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. * Makefile.in: Regenerate. + * configure.ac (bfd_s12z_arch): Correct the dependencies. * configure: Regenerate. - * po/POTFILES.in: Regenerate. -2018-04-16 Alan Modra - - * configure.ac: Remove we32k support. - * configure: Regenerate. - -2018-04-16 Alan Modra - - * Makefile.am: Remove m88k support. - * configure.ac: Likewise. - * disassemble.c: Likewise. - * disassemble.h: Likewise. - * m88k-dis.c: Delete. - * Makefile.in: Regenerate. - * configure: Regenerate. - * po/POTFILES.in: Regenerate. - -2018-04-16 Alan Modra - - * Makefile.am: Remove i370 support. - * configure.ac: Likewise. - * disassemble.c: Likewise. - * disassemble.h: Likewise. - * i370-dis.c: Delete. - * i370-opc.c: Delete. - * Makefile.in: Regenerate. - * configure: Regenerate. - * po/POTFILES.in: Regenerate. - -2018-04-16 Alan Modra - - * Makefile.am: Remove h8500 support. - * configure.ac: Likewise. - * disassemble.c: Likewise. - * disassemble.h: Likewise. - * h8500-dis.c: Delete. - * h8500-opc.h: Delete. - * Makefile.in: Regenerate. - * configure: Regenerate. - * po/POTFILES.in: Regenerate. - -2018-04-16 Alan Modra - - * configure.ac: Remove tahoe support. - * configure: Regenerate. - -2018-04-15 H.J. Lu - - * i386-dis.c (prefix_table): Replace Em with Edq on tpause and - umwait. - * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in - 64-bit mode. - * i386-tbl.h: Regenerated. - -2018-04-11 Igor Tsimbalist - - * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6, - PREFIX_MOD_1_0FAE_REG_6. - (va_mode): New. - (OP_E_register): Use va_mode. - * i386-dis-evex.h (prefix_table): - New instructions (see prefixes above). - * i386-gen.c (cpu_flag_init): Add WAITPKG. - (cpu_flags): Likewise. - * i386-opc.h (enum): Likewise. - (i386_cpu_flags): Likewise. - * i386-opc.tbl: Add umonitor, umwait, tpause. - * i386-init.h: Regenerate. - * i386-tbl.h: Likewise. - -2018-04-11 Alan Modra - - * opcodes/i860-dis.c: Delete. - * opcodes/i960-dis.c: Delete. - * Makefile.am: Remove i860 and i960 support. - * configure.ac: Likewise. - * disassemble.c: Likewise. - * disassemble.h: Likewise. - * Makefile.in: Regenerate. - * configure: Regenerate. - * po/POTFILES.in: Regenerate. - -2018-04-04 H.J. Lu - - PR binutils/23025 - * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w - to 0. - (print_insn): Clear vex instead of vex.evex. - -2018-04-04 Nick Clifton - - * po/es.po: Updated Spanish translation. - -2018-03-28 Jan Beulich - - * i386-gen.c (opcode_modifiers): Delete VecESize. - * i386-opc.h (VecESize): Delete. - (struct i386_opcode_modifier): Delete vecesize. - * i386-opc.tbl: Drop VecESize. - * i386-tlb.h: Re-generate. - -2018-03-28 Jan Beulich - - * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8, - BROADCAST_1TO4, BROADCAST_1TO2): Delete. - (struct i386_opcode_modifier): Shrink broadcast field to 1 bit. - * i386-opc.tbl: Replace Broadcast= by Broadcast. - * i386-tlb.h: Re-generate. - -2018-03-28 Jan Beulich - - * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi): - Fold AVX512 forms - * i386-tlb.h: Re-generate. - -2018-03-28 Jan Beulich - - * i386-dis.c (prefix_table): Drop Y for cvt*2si. - (vex_len_table): Drop Y for vcvt*2si. - (putop): Replace plain 'Y' handling by abort(). - -2018-03-28 Nick Clifton - - PR 22988 - * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx - instructions with only a base address register. - * aarch64-opc.c (operand_general_constraint_met_p): Add code to - handle AARHC64_OPND_SVE_ADDR_R. - (aarch64_print_operand): Likewise. - * aarch64-asm-2.c: Regenerate. - * aarch64_dis-2.c: Regenerate. - * aarch64-opc-2.c: Regenerate. - -2018-03-22 Jan Beulich - - * i386-opc.tbl: Drop VecESize from register only insn forms and - memory forms not allowing broadcast. - * i386-tlb.h: Re-generate. - -2018-03-22 Jan Beulich - - * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*, - vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*, - sha256*): Drop Disp. - -2018-03-22 Jan Beulich - - * i386-dis.c (EbndS, bnd_swap_mode): New. - (prefix_table): Use EbndS. - (OP_E_register, OP_E_memory): Also handle bnd_swap_mode. - * i386-opc.tbl (bndmov): Move misplaced Load. - * i386-tlb.h: Re-generate. - -2018-03-22 Jan Beulich - - * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate - templates allowing memory operands and folded ones for register - only flavors. - * i386-tlb.h: Re-generate. - -2018-03-22 Jan Beulich - - * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and - 256-bit templates. Drop redundant leftover Disp. - * i386-tlb.h: Re-generate. - -2018-03-14 Kito Cheng - - * riscv-opc.c (riscv_insn_types): New. - -2018-03-13 Nick Clifton - - * po/pt_BR.po: Updated Brazilian Portuguese translation. - -2018-03-08 H.J. Lu - - * i386-opc.tbl: Add Optimize to clr. - * i386-tbl.h: Regenerated. - -2018-03-08 H.J. Lu - - * i386-gen.c (opcode_modifiers): Remove OldGcc. - * i386-opc.h (OldGcc): Removed. - (i386_opcode_modifier): Remove oldgcc. - * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp - instructions for old (<= 2.8.1) versions of gcc. - * i386-tbl.h: Regenerated. - -2018-03-08 Jan Beulich - - * i386-opc.h (EVEXDYN): New. - * i386-opc.tbl: Fold various AVX512VL templates. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps, - vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups, - vpexpandd, vpexpandq): Fold AFX512VF templates. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb): - Fold 128- and 256-bit VEX-encoded templates. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps, - vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups, - vpexpandd, vpexpandq): Fold AVX512F templates. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and - 64-bit templates. Drop Disp. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128- - and 256-bit templates. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (cmpxchg8b): Add NoRex64. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx): - Drop NoAVX. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-gen.c (opcode_modifiers): Delete FloatD. - * i386-opc.h (FloatD): Delete. - (struct i386_opcode_modifier): Delete floatd. - * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace - FloatD by D. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (vmovd): Disallow Qword memory operands. - * i386-tlb.h: Re-generate. - -2018-03-08 Jan Beulich - - * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory - forms. - * i386-tlb.h: Re-generate. - -2018-03-07 Alan Modra - - * disassemble.c (disassembler): Use bfd_arch_powerpc entry for - bfd_arch_rs6000. - * disassemble.h (print_insn_rs6000): Delete. - * ppc-dis.c (powerpc_init_dialect): Handle rs6000. - (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000. - (print_insn_rs6000): Delete. - -2018-03-03 Alan Modra - - * sysdep.h (opcodes_error_handler): Define. - (_bfd_error_handler): Declare. - * Makefile.am: Remove stray #. - * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT - EDIT" comment. - * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, - * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, - * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use - opcodes_error_handler to print errors. Standardize error messages. - * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, - and include opintl.h. - * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. - * i386-gen.c: Standardize error messages. - * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. - * Makefile.in: Regenerate. - * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, - * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, - * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, - * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, - * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, - * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, - * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, - * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, - * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, - * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, - * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, - * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, - * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate. - -2018-03-01 H.J. Lu - - * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512 - vpsub[bwdq] instructions. - * i386-tbl.h: Regenerated. - -2018-03-01 Alan Modra - - * configure.ac (ALL_LINGUAS): Sort. - * configure: Regenerate. - -2018-02-27 Thomas Preud'homme - - * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY - macro by assignements. - -2018-02-27 H.J. Lu - - PR gas/22871 - * i386-gen.c (opcode_modifiers): Add Optimize. - * i386-opc.h (Optimize): New enum. - (i386_opcode_modifier): Add optimize. - * i386-opc.tbl: Add "Optimize" to "mov $imm, reg", - "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem", - "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem", - "movq $imm, reg" and AVX256 and AVX512 versions of vandnps, - vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor, - vpxord and vpxorq. - * i386-tbl.h: Regenerated. - -2018-02-26 Alan Modra - - * crx-dis.c (getregliststring): Allocate a large enough buffer - to silence false positive gcc8 warning. - -2018-02-22 Shea Levy - - * disassemble.c (ARCH_riscv): Define if ARCH_all. - -2018-02-22 H.J. Lu - - * i386-opc.tbl: Add {rex}, - * i386-tbl.h: Regenerated. - -2018-02-20 Maciej W. Rozycki - - * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case. - (mips16_opcodes): Replace `M' with `m' for "restore". - -2018-02-19 Thomas Preud'homme - - * arm-dis.c (thumb_opcodes): Fix BXNS mask. - -2018-02-13 Maciej W. Rozycki - - * wasm32-dis.c (print_insn_wasm32): Rename `index' local - variable to `function_index'. - -2018-02-13 Nick Clifton - - PR 22823 - * metag-dis.c (print_fmmov): Double buffer size to avoid warning - about truncation of printing. - -2018-02-12 Henry Wong - - * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. - -2018-02-05 Nick Clifton - - * po/pt_BR.po: Updated Brazilian Portuguese translation. - -2018-01-23 Igor Tsimbalist - - * i386-dis.c (enum): Add pconfig. - * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. - (cpu_flags): Add CpuPCONFIG. - * i386-opc.h (enum): Add CpuPCONFIG. - (i386_cpu_flags): Add cpupconfig. - * i386-opc.tbl: Add PCONFIG instruction. - * i386-init.h: Regenerate. - * i386-tbl.h: Likewise. - -2018-01-23 Igor Tsimbalist - - * i386-dis.c (enum): Add PREFIX_0F09. - * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. - (cpu_flags): Add CpuWBNOINVD. - * i386-opc.h (enum): Add CpuWBNOINVD. - (i386_cpu_flags): Add cpuwbnoinvd. - * i386-opc.tbl: Add WBNOINVD instruction. - * i386-init.h: Regenerate. - * i386-tbl.h: Likewise. - -2018-01-17 Jim Wilson - - * riscv-opc.c (riscv_opcodes) : Use z instead of 0. - -2018-01-17 Igor Tsimbalist - - * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. - Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, - CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. - (cpu_flags): Add CpuIBT, CpuSHSTK. - * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. - (i386_cpu_flags): Add cpuibt, cpushstk. - * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. - * i386-init.h: Regenerate. - * i386-tbl.h: Likewise. - -2018-01-16 Nick Clifton - - * po/pt_BR.po: Updated Brazilian Portugese translation. - * po/de.po: Updated German translation. - -2018-01-15 Jim Wilson - - * riscv-opc.c (match_c_nop): New. - (riscv_opcodes) : Handle an addi that compresses to c.nop. - -2018-01-15 Nick Clifton - - * po/uk.po: Updated Ukranian translation. - -2018-01-13 Nick Clifton - - * po/opcodes.pot: Regenerated. - -2018-01-13 Nick Clifton - - * configure: Regenerate. - -2018-01-13 Nick Clifton - - 2.30 branch created. - -2018-01-11 Igor Tsimbalist - - * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. - * i386-tbl.h: Regenerate. - -2018-01-10 Jan Beulich - - * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift. - * i386-tbl.h: Re-generate. - -2018-01-10 Jan Beulich - - * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, - vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub, - vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew, - vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw, - vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust - Disp8MemShift of AVX512VL forms. - * i386-tbl.h: Re-generate. - -2018-01-09 Jim Wilson - - * riscv-dis.c (maybe_print_address): If base_reg is zero, - then the hi_addr value is zero. - -2018-01-09 James Greenhalgh - - * arm-dis.c (arm_opcodes): Add csdb. - (thumb32_opcodes): Add csdb. - -2018-01-09 James Greenhalgh - - * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". - * aarch64-asm-2.c: Regenerate. - * aarch64-dis-2.c: Regenerate. - * aarch64-opc-2.c: Regenerate. - -2018-01-08 H.J. Lu - - PR gas/22681 - * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. - Remove AVX512 vmovd with 64-bit operands. - * i386-tbl.h: Regenerated. - -2018-01-05 Jim Wilson - - * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a - jalr. - -2018-01-03 Alan Modra +2019-01-01 Alan Modra Update year range in copyright notice of all files. -2018-01-02 Jan Beulich - - * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM - and OPERAND_TYPE_REGZMM entries. - -For older changes see ChangeLog-2017 +For older changes see ChangeLog-2018 -Copyright (C) 2018 Free Software Foundation, Inc. +Copyright (C) 2019 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright