X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=opcodes%2Fmicromips-opc.c;h=696e2a9c171aefb8d6e68438de3da3c79d3b70df;hb=cd22ee05137b858fead379976d4c51e5cf23d907;hp=4b1cdd77da0d0c63524e7af66c94bff3ccf1741e;hpb=351cdf24d223290b15fa991e5052ec9e9bd1e284;p=thirdparty%2Fbinutils-gdb.git diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index 4b1cdd77da0..696e2a9c171 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -1,5 +1,5 @@ /* micromips-opc.c. microMIPS opcode table. - Copyright (C) 2008-2014 Free Software Foundation, Inc. + Copyright (C) 2008-2020 Free Software Foundation, Inc. Contributed by Chao-ying Fu, MIPS Technologies, Inc. This file is part of the GNU opcodes library. @@ -107,6 +107,7 @@ decode_micromips_operand (const char *p) case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */ case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */ case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */ + case 'J': HINT (10, 16); case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */ case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */ case 'V': INT_ADJ (10, 16, 511, 2, FALSE); /* (-512 .. 511) << 2 */ @@ -158,7 +159,6 @@ decode_micromips_operand (const char *p) case '7': REG (2, 14, ACC); case '8': HINT (6, 14); - case 'B': HINT (10, 16); case 'C': HINT (23, 3); case 'D': REG (5, 11, FP); case 'E': REG (5, 21, COPRO); @@ -202,8 +202,8 @@ decode_micromips_operand (const char *p) #define TRAP INSN_NO_DELAY_SLOT #define LM INSN_LOAD_MEMORY #define SM INSN_STORE_MEMORY -#define COD INSN_COPROC_MOVE_DELAY -#define LCD INSN_LOAD_COPROC_DELAY +#define CM INSN_COPROC_MOVE +#define LC INSN_LOAD_COPROC #define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */ #define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */ @@ -253,6 +253,7 @@ decode_micromips_operand (const char *p) are accepted as 64-bit microMIPS ISA. */ #define I1 INSN_ISA1 #define I3 INSN_ISA3 +#define I36 INSN_ISA32R5 /* MIPS DSP ASE support. */ #define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */ @@ -279,6 +280,10 @@ decode_micromips_operand (const char *p) #define MSA ASE_MSA #define MSA64 ASE_MSA64 +/* eXtended Physical Address (XPA) support. */ +#define XPA ASE_XPA +#define XPAVZ ASE_XPA_VIRT + const struct mips_opcode micromips_opcodes[] = { /* These instructions appear first so that the disassembler will find @@ -296,23 +301,20 @@ const struct mips_opcode micromips_opcodes[] = {"li", "md,mI", 0xec00, 0xfc00, WR_1, 0, I1, 0, 0 }, {"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */ {"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */ -#if 0 -/* Disabled until we can handle 48-bit opcodes. */ -{"li", "s,I", 0x7c0000010000, 0xfc00001f0000, WR_t, 0, I3, 0, 0 }, /* li48 */ -#endif {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 }, {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 }, {"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, +{"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* or */ {"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 }, /* daddu */ {"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* addu */ -{"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* or */ {"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 }, {"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* beq 0, 0 */ {"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* bgez 0 */ +/* BC is next to B so that we easily find it when converting a normal + branch to a compact one. */ +{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1, 0, 0 }, /* beqzc 0 */ {"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD32, I1, 0, 0 }, /* bgezal 0 */ {"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD16, I1, 0, 0 }, /* bgezals 0 */ -{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1, 0, 0 }, /* beqzc 0 */ - {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, {"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, @@ -371,12 +373,14 @@ const struct mips_opcode micromips_opcodes[] = {"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, 0 }, {"beqz", "md,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, {"beqz", "s,p", 0x94000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, -{"beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 }, {"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 }, {"beq", "md,mz,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* beqz */ {"beq", "mz,md,mE", 0x8c00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* beqz */ {"beq", "s,t,p", 0x94000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, +/* BEQZC is next to BEQ so that we easily find it when converting a normal + branch to a compact one. */ +{"beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 }, {"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 }, {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1, 0, 0 }, {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, @@ -427,12 +431,14 @@ const struct mips_opcode micromips_opcodes[] = {"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1, 0, 0 }, {"bnez", "md,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, {"bnez", "s,p", 0xb4000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, -{"bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 }, {"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 }, {"bne", "md,mz,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* bnez */ {"bne", "mz,md,mE", 0xac00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* bnez */ {"bne", "s,t,p", 0xb4000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, +/* BNEZC is next to BNE so that we easily find it when converting a normal + branch to a compact one. */ +{"bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 }, {"bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 }, {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1, 0, 0 }, {"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 }, @@ -625,10 +631,10 @@ const struct mips_opcode micromips_opcodes[] = {"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, {"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, {"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, -{"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD, 0, I3, 0, 0 }, -{"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD, 0, I3, 0, 0 }, -{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|COD, 0, I3, 0, 0 }, -{"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|COD, 0, I3, 0, 0 }, +{"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I3, 0, 0 }, +{"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I3, 0, 0 }, +{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, +{"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, {"dmfc2", "t,G", 0x00006d3c, 0xfc00ffff, WR_1|RD_C2, 0, I3, 0, 0 }, /*{"dmfc2", "t,G,H", 0x58000283, 0xfc001fff, WR_1|RD_C2, 0, I3, 0, 0 },*/ {"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 }, @@ -686,13 +692,14 @@ const struct mips_opcode micromips_opcodes[] = {"ei", "", 0x0000577c, 0xffffffff, WR_C0, 0, I1, 0, 0 }, {"ei", "s", 0x0000577c, 0xffe0ffff, WR_1|WR_C0, 0, I1, 0, 0 }, {"eret", "", 0x0000f37c, 0xffffffff, NODS, 0, I1, 0, 0 }, +{"eretnc", "", 0x0001f37c, 0xffffffff, NODS, 0, I36, 0, 0 }, {"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 }, {"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, {"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, {"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, {"floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, {"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, -{"hypcall", "B", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, +{"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, {"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 }, {"iret", "", 0x0000d37c, 0xffffffff, NODS, 0, 0, MC, 0 }, {"jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 }, @@ -702,10 +709,6 @@ const struct mips_opcode micromips_opcodes[] = /* This macro is after the real instruction so that it only matches with -minsn32. */ {"jraddiusp", "mP", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I1, 0, 0 }, -{"jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, 0 }, -/* This macro is after the real instruction so that it only matches with - -minsn32. */ -{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, 0 }, {"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb */ {"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs.hb */ {"j", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 }, /* jr */ @@ -717,6 +720,12 @@ const struct mips_opcode micromips_opcodes[] = assembler, but will never match user input (because the line above will match first). */ {"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1, 0, 0 }, +/* JRC is close to JR and J so that we easily find it when converting + a normal jump to a compact one. */ +{"jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, 0 }, +/* This macro is after the real instruction so that it only matches with + -minsn32. */ +{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, 0 }, {"jalr", "mj", 0x45c0, 0xffe0, RD_1|WR_31|UBD, BD32, I1, 0, 0 }, {"jalr", "my,mj", 0x45c0, 0xffe0, RD_2|WR_31|UBD, BD32, I1, 0, 0 }, {"jalr", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, 0 }, @@ -825,13 +834,17 @@ const struct mips_opcode micromips_opcodes[] = {"maddu", "7,s,t", 0x00001abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_1|RD_C0, 0, I1, 0, 0 }, {"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I1, 0, 0 }, -{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD, 0, I1, 0, 0 }, -{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD, 0, I1, 0, 0 }, +{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I1, 0, 0 }, +{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I1, 0, 0 }, {"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, -{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LCD, 0, I1, 0, 0 }, -{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LCD, 0, I1, 0, 0 }, +{"mfhc0", "t,G", 0x000000f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPA, 0 }, +{"mfhc0", "t,G,H", 0x000000f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPA, 0 }, +{"mfhgc0", "t,G", 0x000004f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPAVZ, 0 }, +{"mfhgc0", "t,G,H", 0x000004f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPAVZ, 0 }, +{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 }, +{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 }, {"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, {"mfhi", "mj", 0x4600, 0xffe0, WR_1|RD_HI, 0, I1, 0, 0 }, {"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_1|RD_HI, 0, I1, 0, 0 }, @@ -871,13 +884,17 @@ const struct mips_opcode micromips_opcodes[] = {"msubu", "7,s,t", 0x00003abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, {"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, -{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|COD, 0, I1, 0, 0 }, -{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|COD, 0, I1, 0, 0 }, +{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, +{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, {"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, {"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, {"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, -{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|COD, 0, I1, 0, 0 }, -{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|COD, 0, I1, 0, 0 }, +{"mthc0", "t,G", 0x000002f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 }, +{"mthc0", "t,G,H", 0x000002f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 }, +{"mthgc0", "t,G", 0x000006f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 }, +{"mthgc0", "t,G,H", 0x000006f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 }, +{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, +{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, {"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, {"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_1|WR_HI, 0, I1, 0, 0 }, {"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_1|WR_HI, 0, 0, D32, 0 }, @@ -967,7 +984,7 @@ const struct mips_opcode micromips_opcodes[] = {"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1, 0, 0 }, {"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1, 0, 0 }, {"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1, 0, 0 }, -{"sdbbp", "B", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, +{"sdbbp", "+J", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, {"sdc1", "T,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 }, {"sdc1", "E,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 }, {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, @@ -1061,16 +1078,16 @@ const struct mips_opcode micromips_opcodes[] = {"invalidate", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */ {"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, {"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I1, 0, 0 }, -{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, +{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, {"sync", "", 0x00006b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, {"sync", "1", 0x00006b7c, 0xffe0ffff, NODS, 0, I1, 0, 0 }, {"synci", "o(b)", 0x42000000, 0xffe00000, RD_2|SM, 0, I1, 0, 0 }, {"syscall", "", 0x00008b7c, 0xffffffff, TRAP, 0, I1, 0, 0 }, -{"syscall", "B", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, +{"syscall", "+J", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, {"teqi", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, {"teq", "s,t", 0x0000003c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, {"teq", "s,t,|", 0x0000003c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, @@ -1125,7 +1142,7 @@ const struct mips_opcode micromips_opcodes[] = {"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, 0 }, {"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, 0 }, {"wait", "", 0x0000937c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"wait", "B", 0x0000937c, 0xfc00ffff, NODS, 0, I1, 0, 0 }, +{"wait", "+J", 0x0000937c, 0xfc00ffff, NODS, 0, I1, 0, 0 }, {"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_2, 0, I1, 0, 0 }, {"wsbh", "t,r", 0x00007b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, {"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 },