[Morello] LDR immediate

[Morello] LDR immediate

The 17-bit signed offset needs to be 16-byte aligned, but the
PCC-relative address resolution rounds down the final address to the
16-byte boundary.  Due to this, disassembly of the instruction will
show as if it is loading from the middle of an object.

bfd/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add
	LD_PREL_LO17.
	(elfNN_aarch64_final_link_relocate,
	elfNN_aarch64_check_relocs): Likewise.
	* elfxx-aarch64.c (reencode_ld_lit_ofs_17): New function.
	(_bfd_aarch64_elf_put_addend,
	_bfd_aarch64_elf_resolve_relocation): Add LD_PREL_LO17.
	* libbfd.h (bfd_reloc_code_real_names): Add
	BFD_RELOC_MORELLO_LD_LO17_PCREL.
	* reloc.c: Add BFD_RELOC_AARCH64_LD_LO17_PCREL.
	* bfd-in2.h: Regenerate.

gas/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* config/tc-aarch64.c (encode_ld_lit_ofs_17): New function.
	(parse_operands, programmer_friendly_fixup, md_apply_fix): Add
	ADDR_PCREL17.

include/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* elf/aarch64.h: New relocation R_MORELLO_LD_PREL_LO17.
	* opcode/aarch64.h (aarch64_opnd): Add ADDR_PCREL17.
	(aarch64_op): Add OP_LDR_LIT_2.

opcodes/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (fields): Add imm17.
	(operand_general_constraint_met_p, aarch64_print_operand): Add
	ADDR_PCREL17.
	* aarch64-opc.h (aarch64_field_kind): Add FLD_imm17.
	* aarch64-tbl.h (QL2_A64C_CA_PCREL): New macro.
	(aarch64_opcode_table): New instruction.
	(AARCH64_OPERANDS): New operand.