]> git.ipfire.org Git - thirdparty/gcc.git/commit - gcc/config/riscv/riscv-protos.h
RISC-V: Add vector psabi checking.
authorYanzhang Wang <yanzhang.wang@intel.com>
Tue, 13 Jun 2023 02:46:40 +0000 (10:46 +0800)
committerPan Li <pan2.li@intel.com>
Tue, 13 Jun 2023 11:34:38 +0000 (19:34 +0800)
commit1d4d302acd915a81f4b7d7a6db44999531f2fd31
treeada983d0a32ee276936ab33413b90abad4f3dfef
parentd5c58ad1ebaff924c2546df074174cffb128feb8
RISC-V: Add vector psabi checking.

This patch adds support to check function's argument or return is vector type
and throw warning if yes.

There're two exceptions,
  - The vector_size attribute.
  - The intrinsic functions.

Some cases that need to add -Wno-psabi to ignore the warning.

gcc/ChangeLog:

* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
warning flag if func is not builtin
* config/riscv/riscv.cc
(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
(riscv_arg_has_vector): Determine whether the arg is vector type.
(riscv_pass_in_vector_p): Check the vector type param is passed by value.
(riscv_init_cumulative_args): The same as header.
(riscv_get_arg_info): Add the checking.
(riscv_function_value): Check the func return and set warning flag
* config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
determine whether warning psabi or not.

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/pr109244.C: Add the -Wno-psabi.
* g++.target/riscv/rvv/base/pr109535.C: Same
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Same
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Same
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Same
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Same
* gcc.target/riscv/rvv/base/pr110109-2.c: Same
* gcc.target/riscv/rvv/base/scalar_move-9.c: Same
* gcc.target/riscv/rvv/base/spill-10.c: Same
* gcc.target/riscv/rvv/base/spill-11.c: Same
* gcc.target/riscv/rvv/base/spill-9.c: Same
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Same
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Same
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Same
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Same
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Same
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Same
* gcc.target/riscv/vector-abi-1.c: New test.
* gcc.target/riscv/vector-abi-2.c: New test.
* gcc.target/riscv/vector-abi-3.c: New test.
* gcc.target/riscv/vector-abi-4.c: New test.
* gcc.target/riscv/vector-abi-5.c: New test.
* gcc.target/riscv/vector-abi-6.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
26 files changed:
gcc/config/riscv/riscv-protos.h
gcc/config/riscv/riscv.cc
gcc/config/riscv/riscv.h
gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
gcc/testsuite/gcc.target/riscv/vector-abi-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/vector-abi-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/vector-abi-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/vector-abi-4.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/vector-abi-5.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/vector-abi-6.c [new file with mode: 0644]