[committed] RISC-V: Infrastructure for instruction fusion

[committed] RISC-V: Infrastructure for instruction fusion

I've been meaning to extract this and upstream it for a long time.  The work is
primarily Philipp from VRULL with one case added by Raphael and light bugfixing
on my part.

Essentially there's 10 distinct fusions supported and they can be selected
individually by building a suitable mask in the uarch tuning structure.
Additional cases can be added -- the bulk of the effort is in recognizing the
two fusible instructions.

The cases supported in this patch are all from the Veyron V1 processor, though
the hope is they will be useful elsewhere.  I would encourage those familiar
with other uarch implementations to enable fusion cases for those uarchs and
extend the set of supported cases if any are missing.

gcc/
	* config/riscv/riscv-protos.h (extract_base_offset_in_addr): Prototype.
	* config/riscv/riscv.cc (riscv_fusion_pairs): New enum.
	(riscv_tune_param): Add fusible_ops field.
	(riscv_tune_param_rocket_tune_info): Initialize new field.
	(riscv_tune_param_sifive_7_tune_info): Likewise.
	(thead_c906_tune_info): Likewise.
	(generic_oo_tune_info): Likewise.
	(optimize_size_tune_info): Likewise.
	(riscv_macro_fusion_p): New function.
	(riscv_fusion_enabled_p): Likewise.
	(riscv_macro_fusion_pair_p): Likewise.
	(TARGET_SCHED_MACRO_FUSION_P): Define.
	(TARGET_SCHED_MACRO_FUSION_PAIR_P): Likewise.
	(extract_base_offset_in_addr): Moved into riscv.cc from...
	* config/riscv/thead.cc: Here.

	Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
	Co-authored-by: Jeff Law <jlaw@ventanamicro.com>