RISC-V: Support RVV VFREDUSUM.VS rounding mode intrinsic API

RISC-V: Support RVV VFREDUSUM.VS rounding mode intrinsic API

This patch would like to support the rounding mode API for the
VFREDUSUM.VS as the below samples.

* __riscv_vfredusum_vs_f32m1_f32m1_rm
* __riscv_vfredusum_vs_f32m1_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class freducop): Add frm_op_type template arg.
	(vfredusum_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfredusum_frm): New intrinsic function def.
	* config/riscv/riscv-vector-builtins-shapes.cc
	(struct reduc_alu_frm_def): New class for frm shape.
	(SHAPE): New declaration.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-redusum.c: New test.