RISC-V: Support RVV VFWNMSAC rounding mode intrinsic API

RISC-V: Support RVV VFWNMSAC rounding mode intrinsic API

This patch would like to support the rounding mode API for the
VFWNMSAC as the below samples.

* __riscv_vfwnmsac_vv_f64m2_rm
* __riscv_vfwnmsac_vv_f64m2_rm_m
* __riscv_vfwnmsac_vf_f64m2_rm
* __riscv_vfwnmsac_vf_f64m2_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class vfwnmsac_frm): New class for frm.
	(vfwnmsac_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfwnmsac_frm): New intrinsic function definition.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-wnmsac.c: New test.