RISC-V: Refactor RVV machine modes

RISC-V: Refactor RVV machine modes

Current machine modes layout is hard to maintain && read && understand.

For a LMUL = 1 SI vector mode:
  1. VNx1SI mode when TARGET_MIN_VLEN = 32.
  2. VNx2SI mode when TARGET_MIN_VLEN = 64.
  3. VNx4SI mode when TARGET_MIN_VLEN = 128.

Such implementation produces redundant machine modes and thus redudant machine description patterns.

Now, this patch refactor machine modes into 3 follow formats:

  1. mask mode: RVVMF64BImode, RVVMF32BImode, ...., RVVM1BImode.
                RVVMF64BImode means such mask mode occupy 1/64 of a RVV M1 reg.
                RVVM1BImode size = LMUL = 1 reg.
  2. non-tuple vector modes:
                RVV<LMUL><BASE_MODE>: E.g. RVVMF8QImode = SEW = 8 && LMUL = MF8
  3. tuple vector modes:
                RVV<LMUL>x<NF><BASE_MODE>.

For example, for SEW = 16, LMUL = MF2 , int mode is always RVVMF4HImode, then adjust its size according to TARGET_MIN_VLEN.

Before this patch,  the machine description patterns: 17551
After this patch, the machine description patterns: 14132 =====> reduce 3K+ patterns.

Regression of gcc/g++ rv32/rv64 all passed.

Ok for trunk?

gcc/ChangeLog:

	* config/riscv/autovec.md
	(len_mask_gather_load<VNX16_QHSD:mode><VNX16_QHSDI:mode>):
	Refactor RVV machine modes.
	(len_mask_gather_load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
	(len_mask_gather_load<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
	(len_mask_gather_load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
	(len_mask_gather_load<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
	(len_mask_gather_load<mode><mode>): Ditto.
	(len_mask_gather_load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
	(len_mask_scatter_store<VNX16_QHSD:mode><VNX16_QHSDI:mode>): Ditto.
	(len_mask_scatter_store<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
	(len_mask_scatter_store<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
	(len_mask_scatter_store<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
	(len_mask_scatter_store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
	(len_mask_scatter_store<mode><mode>): Ditto.
	(len_mask_scatter_store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
	* config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Ditto.
	(ADJUST_NUNITS): Ditto.
	(ADJUST_ALIGNMENT): Ditto.
	(ADJUST_BYTESIZE): Ditto.
	(ADJUST_PRECISION): Ditto.
	(RVV_MODES): Ditto.
	(RVV_WHOLE_MODES): Ditto.
	(RVV_FRACT_MODE): Ditto.
	(RVV_NF8_MODES): Ditto.
	(RVV_NF4_MODES): Ditto.
	(VECTOR_MODES_WITH_PREFIX): Ditto.
	(VECTOR_MODE_WITH_PREFIX): Ditto.
	(RVV_TUPLE_MODES): Ditto.
	(RVV_NF2_MODES): Ditto.
	(RVV_TUPLE_PARTIAL_MODES): Ditto.
	* config/riscv/riscv-v.cc (struct mode_vtype_group): Ditto.
	(ENTRY): Ditto.
	(TUPLE_ENTRY): Ditto.
	(get_vlmul): Ditto.
	(get_nf): Ditto.
	(get_ratio): Ditto.
	(preferred_simd_mode): Ditto.
	(autovectorize_vector_modes): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Ditto.
	* config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Ditto.
	(vbool64_t): Ditto.
	(vbool32_t): Ditto.
	(vbool16_t): Ditto.
	(vbool8_t): Ditto.
	(vbool4_t): Ditto.
	(vbool2_t): Ditto.
	(vbool1_t): Ditto.
	(vint8mf8_t): Ditto.
	(vuint8mf8_t): Ditto.
	(vint8mf4_t): Ditto.
	(vuint8mf4_t): Ditto.
	(vint8mf2_t): Ditto.
	(vuint8mf2_t): Ditto.
	(vint8m1_t): Ditto.
	(vuint8m1_t): Ditto.
	(vint8m2_t): Ditto.
	(vuint8m2_t): Ditto.
	(vint8m4_t): Ditto.
	(vuint8m4_t): Ditto.
	(vint8m8_t): Ditto.
	(vuint8m8_t): Ditto.
	(vint16mf4_t): Ditto.
	(vuint16mf4_t): Ditto.
	(vint16mf2_t): Ditto.
	(vuint16mf2_t): Ditto.
	(vint16m1_t): Ditto.
	(vuint16m1_t): Ditto.
	(vint16m2_t): Ditto.
	(vuint16m2_t): Ditto.
	(vint16m4_t): Ditto.
	(vuint16m4_t): Ditto.
	(vint16m8_t): Ditto.
	(vuint16m8_t): Ditto.
	(vint32mf2_t): Ditto.
	(vuint32mf2_t): Ditto.
	(vint32m1_t): Ditto.
	(vuint32m1_t): Ditto.
	(vint32m2_t): Ditto.
	(vuint32m2_t): Ditto.
	(vint32m4_t): Ditto.
	(vuint32m4_t): Ditto.
	(vint32m8_t): Ditto.
	(vuint32m8_t): Ditto.
	(vint64m1_t): Ditto.
	(vuint64m1_t): Ditto.
	(vint64m2_t): Ditto.
	(vuint64m2_t): Ditto.
	(vint64m4_t): Ditto.
	(vuint64m4_t): Ditto.
	(vint64m8_t): Ditto.
	(vuint64m8_t): Ditto.
	(vfloat16mf4_t): Ditto.
	(vfloat16mf2_t): Ditto.
	(vfloat16m1_t): Ditto.
	(vfloat16m2_t): Ditto.
	(vfloat16m4_t): Ditto.
	(vfloat16m8_t): Ditto.
	(vfloat32mf2_t): Ditto.
	(vfloat32m1_t): Ditto.
	(vfloat32m2_t): Ditto.
	(vfloat32m4_t): Ditto.
	(vfloat32m8_t): Ditto.
	(vfloat64m1_t): Ditto.
	(vfloat64m2_t): Ditto.
	(vfloat64m4_t): Ditto.
	(vfloat64m8_t): Ditto.
	* config/riscv/riscv-vector-switch.def (ENTRY): Ditto.
	(TUPLE_ENTRY): Ditto.
	* config/riscv/riscv-vsetvl.cc (change_insn): Ditto.
	* config/riscv/riscv.cc (riscv_valid_lo_sum_p): Ditto.
	(riscv_v_adjust_nunits): Ditto.
	(riscv_v_adjust_bytesize): Ditto.
	(riscv_v_adjust_precision): Ditto.
	(riscv_convert_vector_bits): Ditto.
	* config/riscv/riscv.h (riscv_v_adjust_nunits): Ditto.
	* config/riscv/riscv.md: Ditto.
	* config/riscv/vector-iterators.md: Ditto.
	* config/riscv/vector.md
	(@pred_indexed_<order>store<VNX16_QHSD:mode><VNX16_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
	(@pred_indexed_<order>store<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
	(@pred_indexed_<order>store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
	(@pred_indexed_<order>store<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
	(@pred_indexed_<order>store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
	(@pred_indexed_<order>store<VNX128_Q:mode><VNX128_Q:mode>): Ditto.
	(@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto.
	(@pred_indexed_<order>load<V1T:mode><VNX1_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto.
	(@pred_indexed_<order>load<V2T:mode><VNX2_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto.
	(@pred_indexed_<order>load<V4T:mode><VNX4_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto.
	(@pred_indexed_<order>load<V8T:mode><VNX8_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto.
	(@pred_indexed_<order>load<V16T:mode><VNX16_QHSI:mode>): Ditto.
	(@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto.
	(@pred_indexed_<order>load<V32T:mode><VNX32_QHI:mode>): Ditto.
	(@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto.
	(@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto.
	(@pred_indexed_<order>store<V1T:mode><VNX1_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto.
	(@pred_indexed_<order>store<V2T:mode><VNX2_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto.
	(@pred_indexed_<order>store<V4T:mode><VNX4_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto.
	(@pred_indexed_<order>store<V8T:mode><VNX8_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto.
	(@pred_indexed_<order>store<V16T:mode><VNX16_QHSI:mode>): Ditto.
	(@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto.
	(@pred_indexed_<order>store<V32T:mode><VNX32_QHI:mode>): Ditto.
	(@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c:
	Adapt test.
	* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c
	: Ditto.
	* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c:
	Ditto.