RISC-V: Implement instruction patterns for ZBA extension.

RISC-V: Implement instruction patterns for ZBA extension.

2021-10-25  Jim Wilson  <jimw@sifive.com>
	    Kito Cheng  <kito.cheng@sifive.com>
	    Jia-Wei Chen  <jiawei@iscas.ac.cn>

gcc/ChangeLog:

	* config/riscv/bitmanip.md (*zero_extendsidi2_bitmanip): New.
	(*shNadd): Ditto.
	(*shNadduw): Ditto.
	(*add.uw): Ditto.
	(*slliuw): Ditto.
	(riscv_rtx_costs): Ditto.
	* config/riscv/riscv.md: Include bitmanip.md
	(type): Add bitmanip bype.
	(zero_extendsidi2): Change to define_expand pattern.
	(*zero_extendsidi2_internal): New.
	(zero_extendsidi2_shifted): Disable for ZBA.

2021-10-25  Kito Cheng  <kito.cheng@sifive.com>
	    Jia-Wei Chen  <jiawei@iscas.ac.cn>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zba-adduw.c: New.
	* gcc.target/riscv/zba-shNadd-01.c: Ditto.
	* gcc.target/riscv/zba-shNadd-02.c: Ditto.
	* gcc.target/riscv/zba-shNadd-03.c: Ditto.
	* gcc.target/riscv/zba-slliuw.c: Ditto.
	* gcc.target/riscv/zba-zextw.c: Ditto.

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Co-authored-by: Jia-Wei Chen <jiawei@iscas.ac.cn>