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RISC-V: Optimize si to di zero-extend followed by left shift.
authorJim Wilson <jimw@sifive.com>
Sun, 31 May 2020 00:04:17 +0000 (17:04 -0700)
committerJim Wilson <jimw@sifive.com>
Sun, 31 May 2020 00:09:15 +0000 (17:09 -0700)
commitd5cdcd5cf2b2920b44836005baceb59d046b6e5a
treebecb1148e911f52560dd5c0367cdd14be5e9c76btree | snapshot
parent9f2e635defba9d697a6c291013b37bd2c7ed91aacommit | diff
RISC-V: Optimize si to di zero-extend followed by left shift.

This is potentially a sequence of 3 shifts, we which optimize to a sequence
of 2 shifts.  This can happen when unsigned int is used for array indexing.

gcc/
* config/riscv/riscv.md (zero_extendsidi2_shifted): New.

gcc/testsuite/
* gcc.target/riscv/zero-extend-5.c: New.
gcc/config/riscv/riscv.md diff | blob | blame | history
gcc/testsuite/gcc.target/riscv/zero-extend-5.c [new file with mode: 0644] blob
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