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re PR target/65710 (Thumb1 ICE caused by no register to spill)
authorVladimir Makarov <vmakarov@redhat.com>
Thu, 9 Apr 2015 19:40:09 +0000 (19:40 +0000)
committerVladimir Makarov <vmakarov@gcc.gnu.org>
Thu, 9 Apr 2015 19:40:09 +0000 (19:40 +0000)
commit8fd827b8e58b04cdefeb3d5c4de4d53566fdc3ff
tree9684a6d40e6a42b869a0f236d04ab6c6882b0ca8tree | snapshot
parentbf1b77dd092bb694be6fb0b1fcc369327db6143fcommit | diff
re PR target/65710 (Thumb1 ICE caused by no register to spill)

2015-04-09  Vladimir Makarov  <vmakarov@redhat.com>

PR target/65710
* lra-int.h (lra_bad_spill_regno_start): New.
* lra.c (lra_bad_spill_regno_start): New.
(lra): Set up lra_bad_spill_regno_start.  Set up
lra_constraint_new_regno_start unconditionally.
* lra-assigns.c (spill_for): Use lra_bad_spill_regno_start for
spill preferences.

From-SVN: r221956
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gcc/lra-assigns.c diff | blob | blame | history
gcc/lra-int.h diff | blob | blame | history
gcc/lra.c diff | blob | blame | history
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