Add support for bitwise reductions

Add support for bitwise reductions

This patch adds support for the SVE bitwise reduction instructions
(ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
REDUC_* operators.

2018-01-13  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
	(reduc_xor_scal_optab): New optabs.
	* doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
	(reduc_xor_scal_@var{m}): Document.
	* doc/sourcebuild.texi (vect_logical_reduc): Likewise.
	* internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
	internal functions.
	* fold-const-call.c (fold_const_call): Handle them.
	* tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
	internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
	* config/aarch64/aarch64-sve.md (reduc_<bit_reduc>_scal_<mode>):
	(*reduc_<bit_reduc>_scal_<mode>): New patterns.
	* config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
	(UNSPEC_XORV): New unspecs.
	(optab): Add entries for them.
	(BITWISEV): New int iterator.
	(bit_reduc_op): New int attributes.

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_vect_logical_reduc):
	New proc.
	* gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
	and add an associated scan-dump test.  Prevent vectorization
	of the first two loops.
	* gcc.dg/vect/vect-reduc-or_2.c: Likewise.
	* gcc.target/aarch64/sve/reduc_1.c: Add AND, IOR and XOR reductions.
	* gcc.target/aarch64/sve/reduc_2.c: Likewise.
	* gcc.target/aarch64/sve/reduc_1_run.c: Likewise.
	(INIT_VECTOR): Tweak initial value so that some bits are always set.
	* gcc.target/aarch64/sve/reduc_2_run.c: Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256624