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(parent: 3bb1af2) | patch
aarch64: Add vector implementations of log routines
authorJoe Ramsay <Joe.Ramsay@arm.com>
Wed, 28 Jun 2023 11:19:38 +0000 (12:19 +0100)
committerSzabolcs Nagy <szabolcs.nagy@arm.com>
Fri, 30 Jun 2023 08:04:22 +0000 (09:04 +0100)
commit78c01a5cbeb6717ffa2d4d66bb90ac5c39bd81a9
tree989c1b12f52fc1886b0b493aa8cc0e01e6fc1d1ftree | snapshot
parent3bb1af20513b8b70b8d404c71fb0956f00f8bf6bcommit | diff
aarch64: Add vector implementations of log routines

Optimised implementations for single and double precision, Advanced
SIMD and SVE, copied from Arm Optimized Routines. Log lookup table
added as HIDDEN symbol to allow it to be shared between AdvSIMD and
SVE variants.

As previously, data tables are used via a barrier to prevent
overly aggressive constant inlining. Special-case handlers are
marked NOINLINE to avoid incurring the penalty of switching call
standards unnecessarily.

Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
15 files changed:
sysdeps/aarch64/fpu/Makefile diff | blob | blame | history
sysdeps/aarch64/fpu/Versions diff | blob | blame | history
sysdeps/aarch64/fpu/bits/math-vector.h diff | blob | blame | history
sysdeps/aarch64/fpu/log_advsimd.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/log_sve.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/logf_advsimd.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/logf_sve.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c diff | blob | blame | history
sysdeps/aarch64/fpu/test-double-sve-wrappers.c diff | blob | blame | history
sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c diff | blob | blame | history
sysdeps/aarch64/fpu/test-float-sve-wrappers.c diff | blob | blame | history
sysdeps/aarch64/fpu/v_log_data.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/vecmath_config.h diff | blob | blame | history
sysdeps/aarch64/libm-test-ulps diff | blob | blame | history
sysdeps/unix/sysv/linux/aarch64/libmvec.abilist diff | blob | blame | history
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