[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.

[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.

The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.

The general form for these instructions is
   <OP> <Hd>, <Hs>, #<imm>

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
	by immediate instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_SSHIFT_H): New.
	(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
	and fcvtzu to the Adv.SIMD scalar shift by immediate group.

Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff