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irqchip/gic-v3-its: Fix access width for gicr_syncr
authorHeyi Guo <guoheyi@huawei.com>
Tue, 25 Feb 2020 09:00:23 +0000 (17:00 +0800)
committerMarc Zyngier <maz@kernel.org>
Sun, 8 Mar 2020 14:25:46 +0000 (14:25 +0000)
commit04d80dbe858d801efbecf3e5172b31b0a3757308
tree6a3bb01026b1cb74232f7e1a121845814388d7a0tree | snapshot
parent47beed513a85b3561e74cbb4dd7af848716fa4e0commit | diff
irqchip/gic-v3-its: Fix access width for gicr_syncr

GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.

Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200225090023.28020-1-guoheyi@huawei.com
drivers/irqchip/irq-gic-v3-its.c diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git