]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: Ignore reserved bits in PTE for RV64
authorGuo Ren <ren_guo@c-sky.com>
Fri, 4 Feb 2022 02:26:54 +0000 (10:26 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:25:52 +0000 (12:25 +1000)
commit05e6ca5e156d1d114d1eb878cae9744cb4a539e3
tree2e4a024c5c68f73b857957c5c3b249afd52e6a6b
parente8f79343cfc886aaa225cec9faf6881f75945209
target/riscv: Ignore reserved bits in PTE for RV64

Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.

1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
   4.4 Sv39: Page-Based 39-bit Virtual-Memory System
   4.5 Sv48: Page-Based 48-bit Virtual-Memory System

2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/cpu_helper.c