[committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model

[committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model

The test for the recently added XiangShan Nanhu microarchitecture is failing
because the scheduler description does not have entries for certain insn types.

I'm adding  branch, jalr, ret and sfb_alu to the scheduler description, that's
enough to get the trivial test to pass.  However, I strongly suspect running
any significant code through the compiler when scheduling for this
microarchitecture will trigger faults.

Basically we have checking now that will fault if we have an insn in the IL
without an associated type or if we have an insn in the IL that does not map to
an insn reservation in the scheduler model.  We were tripping the latter
assertion for one of those branch types.  My suspicion is many insn types
aren't handled by that DFA.

The branch insns were pretty obvious and easy to fix.  But someone with more
experience with the uarch needs to do an audit to ensure that all insn types
map to an insn reservation.

gcc/
	* config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret
	and sfb_alu.