RISC-V: Fix typo in tt-ascalon-d8's pipeline description [PR121878]

RISC-V: Fix typo in tt-ascalon-d8's pipeline description [PR121878]

PR121878 shows a typo in the tt-ascalon-d8's pipeline description that
leads to an ICE.  The problem is that the vector define_insn_reservation
patterns test for scalar modes rather than vector modes, meaning the
insns don't get handled correctly.  We could correct the modes, but given
we could have multiple VLEN values, the number of modes we'd have to check
can be large and mode iterators are not allowed in the mode attribute check.
Instead, I've removed the mode check and replaced it with a test of the
Selected Elenent Width (SEW).

2025-09-09  Peter Bergner  <bergner@tenstorrent.com>

gcc/
	PR target/121878
	* config/riscv/tt-ascalon-d8.md (tt_ascalon_d8_vec_idiv_half): Test the
	Selected Element Width (SEW) rather than the mode.
	(tt_ascalon_d8_vec_idiv_single): Likewise.
	(tt_ascalon_d8_vec_idiv_double): Likewise.
	(tt_ascalon_d8_vec_float_divsqrt_half): Likewise.
	(tt_ascalon_d8_vec_float_divsqrt_single): Likewise.
	(tt_ascalon_d8_vec_float_divsqrt_double): Likewise.

gcc/testsuite/
	PR target/121878
	* gcc.target/riscv/pr121878.c: New test.

Signed-off-by: Peter Bergner <bergner@tenstorrent.com>