]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add support for xtheadvector-specific intrinsics.
authorJun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
Fri, 12 Jan 2024 03:22:41 +0000 (11:22 +0800)
committerChristoph Müllner <christoph.muellner@vrull.eu>
Thu, 18 Jan 2024 14:38:45 +0000 (15:38 +0100)
commit0a41c3e49af36cde6792413051c7054eeccb63fb
tree63ba5036c31a66c2156219eba9488975126aa755
parent2d7205eb2c3b175a86aab92bb652314f308f9c05
RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(struct th_extract_def): Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
* config/riscv/riscv-vector-builtins.h
(enum required_ext): Add new XTheadVector member.
(struct function_group_info): Likewise.
* config/riscv/t-riscv:
Add thead-vector-builtins-functions.def
* config/riscv/thead-vector.md
(@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
(*pred_mov_width<vlmem_op_attr><mode>): Likewise.
(@pred_store_width<vlmem_op_attr><mode>): Likewise.
(@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
(@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
(@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
(@pred_th_extract<mode>): Likewise.
(*pred_th_extract<mode>): Likewise.
* config/riscv/thead-vector-builtins-functions.def: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
15 files changed:
gcc/config/riscv/riscv-vector-builtins-bases.cc
gcc/config/riscv/riscv-vector-builtins-bases.h
gcc/config/riscv/riscv-vector-builtins-shapes.cc
gcc/config/riscv/riscv-vector-builtins-shapes.h
gcc/config/riscv/riscv-vector-builtins.cc
gcc/config/riscv/riscv-vector-builtins.h
gcc/config/riscv/t-riscv
gcc/config/riscv/thead-vector-builtins-functions.def [new file with mode: 0644]
gcc/config/riscv/thead-vector.md
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c [new file with mode: 0644]