RISC-V: Use extension instructions instead of bitwise "and"

RISC-V: Use extension instructions instead of bitwise "and"

In the case where the target supports extension instructions,
it is preferable to use that instead of doing the same in other ways.
For the following case

void foo (unsigned long a, unsigned long* ptr) {
    ptr[0] = a & 0xffffffffUL;
    ptr[1] &= 0xffffffffUL;
}

GCC generates
foo:
        li      a5,-1
        srli    a5,a5,32
        and     a0,a0,a5
        sd      a0,0(a1)
        ld      a4,8(a1)
        and     a5,a4,a5
        sd      a5,8(a1)
        ret

but it will be profitable to generate this one

foo:
  zext.w a0,a0
  sd a0,0(a1)
  lwu a5,8(a1)
  sd a5,8(a1)
  ret

This patch fixes mentioned issue.
It supports HI -> DI, HI->SI and SI -> DI extensions.

gcc/ChangeLog:
	* config/riscv/riscv.md (and<mode>3): New expander.
	(*and<mode>3) New pattern.
	* config/riscv/predicates.md (arith_operand_or_mode_mask): New
	predicate.

gcc/testsuite/ChangeLog:
	* gcc.target/riscv/and-extend-1.c: New test
	* gcc.target/riscv/and-extend-2.c: New test