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(parent: 2eef0bf) | patch
target-arm: Implement ISR_EL1 register
authorPeter Maydell <peter.maydell@linaro.org>
Tue, 15 Apr 2014 18:18:46 +0000 (19:18 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 17 Apr 2014 20:34:05 +0000 (21:34 +0100)
commit1090b9c6ccfe837f1c76dafb7e56031bd7844075
treedcefb350ea9e9d53f395d506c55dd8b2ed14d717tree | snapshot
parent2eef0bf82146034f756d39cb02c8c8dd561a8942commit | diff
target-arm: Implement ISR_EL1 register

Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm/helper.c diff | blob | blame | history
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