RISC-V: Add testcases for form 3 of signed vector SAT_ADD

RISC-V: Add testcases for form 3 of signed vector SAT_ADD

Form 3:
  #define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)                     \
  void __attribute__((noinline))                                       \
  vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T sum;                                                         \
        bool overflow = __builtin_add_overflow (x, y, &sum);           \
        out[i] = overflow ? x < 0 ? MIN : MAX : sum;                   \
      }                                                                \
  }

DEF_VEC_SAT_S_ADD_FMT_3 (int8_t, uint8_t, INT8_MIN, INT8_MAX)

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-10.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-11.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-12.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>