rs6000: Add two peephole patterns for "mr." insn

rs6000: Add two peephole patterns for "mr." insn

When investigating the issue mentioned in PR87871#c30 - if compare
and move pattern benefits before RA, I checked the assembly generated
for SPEC2017 and found that certain insn sequences aren't converted to
"mr." instructions.
Following two sequence are never to be combined to "mr." pattern as
there is no register link between them. This patch adds two peephole2
patterns to convert them to "mr." instructions.

cmp 0,3,0
mr 4,3

mr 4,3
cmp 0,3,0

The patch also creates a new mode iterator which decided by
TARGET_POWERPC64.  This mode iterator is used in "mr." and its split
pattern.  The original P iterator is improper when -m32/-mpowerpc64 is
set.  In this situation, the "mr." should compares the whole 64-bit
register with 0 other than the low 32-bit one.

gcc/
	* config/rs6000/rs6000.md (peephole2 for compare_and_move): New.
	(peephole2 for move_and_compare): New.
	(mode_iterator WORD): New.  Set the mode to SI/DImode by
	TARGET_POWERPC64.
	(*mov<mode>_internal2): Change the mode iterator from P to WORD.
	(split pattern for compare_and_move): Likewise.

gcc/testsuite/
	* gcc.dg/rtl/powerpc/move_compare_peephole_32.c: New.
	* gcc.dg/rtl/powerpc/move_compare_peephole_64.c: New.