]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for mul
authorPan Li <pan2.li@intel.com>
Fri, 19 Sep 2025 06:54:48 +0000 (14:54 +0800)
committerPan Li <pan2.li@intel.com>
Wed, 24 Sep 2025 02:35:07 +0000 (10:35 +0800)
commit1617b9e1bbd967959d1f0cfd428137cf1da1e34c
treec64746b0756ef13a9ca8677e37aa7a84bf9a291e
parent02142e21d98b0f9a70a5fe3fb636d38c01c466d3
RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for mul

Add test case for both the run and asm check of mul based SAT_MUL.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat/sat_u_mul-6-u16-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-6-u16-from-u64.rv32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-6-u16-from-u64.rv64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-6-u32-from-u64.rv32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-6-u32-from-u64.rv64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-6-u8-from-u16.c: New test.
* gcc.target/riscv/sat/sat_u_mul-6-u8-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-6-u8-from-u64.rv32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-6-u8-from-u64.rv64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-6-u32-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u16.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
15 files changed:
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u64.rv32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u64.rv64.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u32-from-u64.rv32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u32-from-u64.rv64.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u16.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u64.rv32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u64.rv64.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u64.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u32-from-u64.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u16.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u64.c [new file with mode: 0644]