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author	Monk Chiang <monk.chiang@sifive.com>
	Fri, 3 Feb 2023 04:58:51 +0000 (12:58 +0800)
committer	Kito Cheng <kito.cheng@sifive.com>
	Fri, 3 Feb 2023 06:57:42 +0000 (14:57 +0800)
commit	167b04b9b8a2becfd23b8ccf7f09016bbd013e12
tree	ea95dfd51458848dd1080f777c1d85f3df909728	tree \| snapshot
parent	f3a10f4fff3d6751aa65df58b8629f84a0c04545	commit \| diff

RISC-V: Remove unnecessary register class.

Avoid VL_REGS, VTYPE_REGS join register allocation.

gcc/ChangeLog:

* config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class.
* config/riscv/riscv.cc: Ditto.

gcc/config/riscv/riscv.cc		diff \| blob \| blame \| history
gcc/config/riscv/riscv.h		diff \| blob \| blame \| history

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