RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized

RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized

The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not.  But the rtl pass expand is somehow
impressionable by the middle-end change or debug information.  Like
below new appearance recently.

Replacing Expressions
_5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call]

After that we need to adjust the dump check time and again.  This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Take
	tree-optimized pass for standard name check, and adjust the times.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>