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(parent: 638b752) | patch
pci-bridge/cxl_downstream: Add a CXL switch downstream port
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Thu, 16 Jun 2022 14:51:25 +0000 (15:51 +0100)
committerMichael S. Tsirkin <mst@redhat.com>
Thu, 16 Jun 2022 16:54:57 +0000 (12:54 -0400)
commit18cef1c6a5a37710a2e5876fed2445849f31e321
treea89e89a03c491f4f9c83e020b61e639dddf61091tree | snapshot
parent638b752da30a9daffb0c92166937a0cb777f9e23commit | diff
pci-bridge/cxl_downstream: Add a CXL switch downstream port

Emulation of a simple CXL Switch downstream port.
The Device ID has been allocated for this use.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220616145126.8002-3-Jonathan.Cameron@huawei.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
hw/cxl/cxl-host.c diff | blob | blame | history
hw/pci-bridge/cxl_downstream.c [new file with mode: 0644] blob
hw/pci-bridge/meson.build diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git