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(parent: 837f7df) | patch
riscv: Provide vector crypto implementation of AES-CTR mode.
authorPhoebe Chen <phoebe.chen@sifive.com>
Tue, 12 Sep 2023 14:02:30 +0000 (07:02 -0700)
committerHugo Landau <hlandau@openssl.org>
Thu, 26 Oct 2023 14:55:50 +0000 (15:55 +0100)
commit18ed3a58b01f8f1affdedced1f4f62447b7df9f9
treee478245a0b1f91a50cf314e76aa50ad6dc0adaa1tree | snapshot
parent837f7df8c0a4122ae95b0859329c9327a44e1764commit | diff
riscv: Provide vector crypto implementation of AES-CTR mode.

Support zvbb-zvkned based rvv AES-128/192/256-CTR encryption.

Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Hugo Landau <hlandau@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/21923)
crypto/aes/asm/aes-riscv64-zvkb-zvkned.pl [new file with mode: 0644] blob
crypto/aes/build.info diff | blob | blame | history
include/crypto/aes_platform.h diff | blob | blame | history
providers/implementations/ciphers/cipher_aes_hw_rv64i.inc diff | blob | blame | history
Mirror of https://github.com/openssl/openssl.git