RISC-V: Disable unsupported vsext/vzext patterns for XTheadVector.

RISC-V: Disable unsupported vsext/vzext patterns for XTheadVector.

XThreadVector does not support the vsext/vzext instructions; however,
due to the reuse of RVV optimizations, it may generate these instructions
in certain cases. To prevent the error "Unknown opcode 'th.vsext.vf2',"
we should disable these patterns.

V2:
Change the value of dg-do in the test case from assemble to compile, and
remove the -save-temps option.

gcc/ChangeLog:

	* config/riscv/vector.md: Disable vsext/vzext for XTheadVector.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xtheadvector/vsext.c: New test.
	* gcc.target/riscv/rvv/xtheadvector/vzext.c: New test.