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(parent: 087b051) | patch
target/riscv: Only flush TLB if SATP.ASID changes
authorJonathan Behrens <jonathan@fintelia.io>
Wed, 8 May 2019 17:38:35 +0000 (13:38 -0400)
committerPalmer Dabbelt <palmer@sifive.com>
Fri, 24 May 2019 19:09:25 +0000 (12:09 -0700)
commit1e0d985fa9136a563168a3da66f3d17820404ee2
treeedfeec3a5ef58a435424087a9cfa8f5020429127tree
parent087b051a51a0c2a5bc1e8d435a484a8896b4176bcommit | diff
target/riscv: Only flush TLB if SATP.ASID changes

There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/csr.c diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git