]> git.ipfire.org Git - thirdparty/qemu.git/commit
hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation
authorPeter Maydell <peter.maydell@linaro.org>
Fri, 1 Nov 2024 16:11:25 +0000 (16:11 +0000)
committerCédric Le Goater <clg@redhat.com>
Mon, 4 Nov 2024 10:33:13 +0000 (11:33 +0100)
commit1f67508c1cc0223664f566980228f5a5090ffa2f
tree7ffa5b16feaba5cfbf5b475061143cb4c41037a7
parented680effe33b9d4ba5d0715a689c871f6b681bf4
hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation

When calculating the index into the GIC's GPIO array for per-CPU
interrupts, we have to start with the number of SPIs.  The code
currently hard-codes this to 'NUM_IRQS = 256'.  However the number of
SPIs is set separately and implicitly by the value of
AST2700_MAX_IRQ, which is the number of SPIs plus 32 (since it is
what we set the GIC num-irq property to).

Define AST2700_MAX_IRQ as the total number of SPIs; this brings
AST2700 into line with AST2600, which defines AST2600_MAX_IRQ as the
number of SPIs not including the 32 internal interrupts.  We can then
use AST2700_MAX_IRQ instead of the hardcoded 256.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/arm/aspeed_ast27x0.c