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(parent: 97a72bc) | patch
ARM: socfpga: Add ArriaV ST/SX ID
authorMarek Vasut <marex@denx.de>
Wed, 20 Nov 2019 21:40:19 +0000 (22:40 +0100)
committerMarek Vasut <marex@denx.de>
Mon, 25 Nov 2019 12:12:56 +0000 (13:12 +0100)
commit2007a730eef83421cc6ca3c1875fa0e0b4d4712e
tree177ad898feb73bd25877e4c979c0509e222d5ad8tree | snapshot
parent97a72bc28613733572b9632a51ab9c8680d45406commit | diff
ARM: socfpga: Add ArriaV ST/SX ID

Add new FPGA ID for ArriaV ST/D3 or SX/B3 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
arch/arm/mach-socfpga/misc_gen5.c diff | blob | blame | history
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