]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/i386: Add PerfMonV2 feature bit
authorSandipan Das <sandipan.das@amd.com>
Thu, 24 Oct 2024 22:18:21 +0000 (17:18 -0500)
committerPaolo Bonzini <pbonzini@redhat.com>
Thu, 31 Oct 2024 17:28:32 +0000 (18:28 +0100)
commit209b0ac12074341d0093985eb9ad3e7edb252ce5
tree6f1e22f4719c781cd7d90bf5ea166790edd6e5da
parent9c882ad4dc96f658ff9f92b88b3749d0398e6fa2
target/i386: Add PerfMonV2 feature bit

CPUID leaf 0x80000022, i.e. ExtPerfMonAndDbg, advertises new performance
monitoring features for AMD processors. Bit 0 of EAX indicates support
for Performance Monitoring Version 2 (PerfMonV2) features. If found to
be set during PMU initialization, the EBX bits can be used to determine
the number of available counters for different PMUs. It also denotes the
availability of global control and status registers.

Add the required CPUID feature word and feature bit to allow guests to
make use of the PerfMonV2 features.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/a96f00ee2637674c63c61e9fc4dee343ea818053.1729807947.git.babu.moger@amd.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/i386/cpu.c
target/i386/cpu.h