RISC-V: Fix wrong LMUL when only implict zve32f.

RISC-V: Fix wrong LMUL when only implict zve32f.

According to Section 3.4.2, Vector Register Grouping, in the RISC-V
Vector Specification, the rule for LMUL is LMUL >= SEW/ELEN

Changes since V2:
- Add check on vector-iterators.md
- Add one more testcase to check the VLS use correct mode.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc: Add restrict for insert LMUL.
	* config/riscv/riscv-vector-builtins-types.def:
	Use RVV_REQUIRE_ELEN_64 to check LMUL number.
	* config/riscv/riscv-vector-switch.def: Likewise.
	* config/riscv/vector-iterators.md: Check TARGET_VECTOR_ELEN_64
	rather than "TARGET_MIN_VLEN > 32" for all iterator.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr111391-2.c: Update test.
	* gcc.target/riscv/rvv/base/abi-14.c: Update test.
	* gcc.target/riscv/rvv/base/abi-16.c: Update test.
	* gcc.target/riscv/rvv/base/abi-18.c: Update test.
	* gcc.target/riscv/rvv/base/vsetvl_zve32-1.c: New test.
	* gcc.target/riscv/rvv/base/vsetvl_zve32-2.c: New test.

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>