]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: Add itrigger support when icount is not enabled
authorLIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Thu, 13 Oct 2022 06:29:43 +0000 (14:29 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 6 Jan 2023 00:42:55 +0000 (10:42 +1000)
commit2c9d747121aa9f8f0494b9e3136a22a1c3a8b2a3
tree8cc47a138ce0357f917299a47c199dddeb2036e8
parentfb3f3730e405e2451dffc03c572037c2e0bd44c0
target/riscv: Add itrigger support when icount is not enabled

When icount is not enabled, there is no API in QEMU that can get the
guest instruction number.

Translate the guest code in a way that each TB only has one instruction.
After executing the instruction, decrease the count by 1 until it reaches 0
where the itrigger fires.

Note that only when priviledge matches the itrigger configuration,
the count will decrease.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-2-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_helper.c
target/riscv/debug.c
target/riscv/debug.h
target/riscv/helper.h
target/riscv/insn_trans/trans_privileged.c.inc
target/riscv/insn_trans/trans_rvi.c.inc
target/riscv/insn_trans/trans_rvv.c.inc
target/riscv/translate.c