RISC-V: Support const vector expansion with step vector with base != 0

RISC-V: Support const vector expansion with step vector with base != 0

Currently, we are able to generate step vector with base == 0:
 { 0, 0, 2, 2, 4, 4, ... }

ASM:

vid
vand

However, we do wrong for step vector with base != 0:
{ 1, 1, 3, 3, 5, 5, ... }

Before this patch, such case will run fail.

After this patch, we are able to pass the testcase and generate the step vector with asm:

vid
vand
vadd

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector): Fix stepped vector
	with base != 0.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/partial/slp-17.c: New test.
	* gcc.target/riscv/rvv/autovec/partial/slp-18.c: New test.
	* gcc.target/riscv/rvv/autovec/partial/slp-19.c: New test.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: New test.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: New test.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: New test.