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i386: Allow MMX register modes in SSE registers
authorhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 15 May 2019 15:02:54 +0000 (15:02 +0000)
committerhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 15 May 2019 15:02:54 +0000 (15:02 +0000)
commit2d2ce81830183cbd30ffcea0a0eb848707bfe9ff
treeb6d4e739c2425a70e5b2bb5093622885b42b5af3tree | snapshot
parent88319664bf8c5f968e07a5cf0622ef31bfd4a3a4commit | diff
i386: Allow MMX register modes in SSE registers

In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW.  We can use SSE2 to support MMX register modes.

PR target/89021
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
* config/i386/i386.c (ix86_set_reg_reg_cost): Add support for
TARGET_MMX_WITH_SSE with VALID_MMX_REG_MODE.
(ix86_vector_mode_supported_p): Likewise.
* config/i386/i386.h (TARGET_MMX_WITH_SSE): New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@271213 138bc75d-0d04-0410-961f-82ee72b054a4
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gcc/config/i386/i386-c.c diff | blob | blame | history
gcc/config/i386/i386.c diff | blob | blame | history
gcc/config/i386/i386.h diff | blob | blame | history
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