[RISC-V] shift+and+shift for logical and synthesis

[RISC-V] shift+and+shift for logical and synthesis

The next chunk of Shreya's work.

For this expansion we want to detect cases when the mask fits in a simm12 after
shifting right by the number of trailing zeros in the mask.

In that case we can synthesize the AND with a shift right, andi and shift left.
I saw this case come up when doing some experimentation with mvconst_internal
removed.

This doesn't make any difference in spec right now, mvconst_internal will turn
the sequence back into a constant load + and with register. But Shreya and I
have reviewed the .expand dump on hand written tests and verified we're getting
the synthesis we want.

Tested on riscv32-elf and riscv64-elf.  Waiting on upstream CI's verdict before
moving forward.

gcc/
	* config/riscv/riscv.cc (synthesize_and): Use a srl+andi+sll
	sequence when the mask fits in a simm12 after shifting by the
	number of trailing zeros.

	Co-authored-by: Jeff Law <jlaw@ventanamicro.com>