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clk: tegra: Fix PLLP rate table
authorGabe Black <gabeblack@chromium.org>
Fri, 27 Dec 2013 00:44:21 +0000 (16:44 -0800)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Mon, 17 Feb 2014 14:18:02 +0000 (16:18 +0200)
commit2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a
tree80532460e0a1598b4382f2e7a42287c075f758c7tree | snapshot
parent2edf3e035302776e4756e446baf3b6c7b94c3698commit | diff
clk: tegra: Fix PLLP rate table

This table had settings for 216MHz, but PLLP is (and is supposed to be)
configured at 408MHz.  If that table is used and PLLP_BASE_OVRRIDE is
not set, the kernel will panic in clk_pll_recalc_rate().

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
drivers/clk/tegra/clk-tegra124.c diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git