]> git.ipfire.org Git - thirdparty/linux.git/commit
Merge patch series "riscv: Add bfloat16 instruction support"
authorAlexandre Ghiti <alexghiti@rivosinc.com>
Tue, 18 Mar 2025 11:52:54 +0000 (11:52 +0000)
committerAlexandre Ghiti <alexghiti@rivosinc.com>
Tue, 18 Mar 2025 11:52:54 +0000 (11:52 +0000)
commit2f2cd9f33435834a6dfca406bb121ff9a885fb23
treecf3e346c7af0faa8e30455f7cd9f875bfc8c4656
parentd9708b1931fc0ebb21cd94a56283d09222847749
parenta4863e002cf0dd6fb2f06796f16d7bc0974e9845
Merge patch series "riscv: Add bfloat16 instruction support"

Inochi Amaoto <inochiama@gmail.com> says:

Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.

* patches from https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com:
  riscv: hwprobe: export bfloat16 ISA extension
  riscv: add ISA extension parsing for bfloat16 ISA extension
  dt-bindings: riscv: add bfloat16 ISA extension description

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com
Documentation/arch/riscv/hwprobe.rst
Documentation/devicetree/bindings/riscv/extensions.yaml
arch/riscv/include/uapi/asm/hwprobe.h
arch/riscv/kernel/cpufeature.c
arch/riscv/kernel/sys_hwprobe.c