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(parent: 3314efd) | patch
hw/pci-bridge/cxl_downstream: Set default link width and link speed
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Mon, 23 Oct 2023 16:07:58 +0000 (17:07 +0100)
committerMichael S. Tsirkin <mst@redhat.com>
Tue, 7 Nov 2023 08:39:11 +0000 (03:39 -0500)
commit314f5033c639ebe8218078a17513935747f15d9d
treef3f44e2454aa57e2e01dc25f2d43f79d355d39e3tree | snapshot
parent3314efd276ada18cc0b8beb70b8943f8deb872b7commit | diff
hw/pci-bridge/cxl_downstream: Set default link width and link speed

Without these being set the PCIE Link Capabilities register has
invalid values in these two fields.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-10-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
hw/pci-bridge/cxl_downstream.c diff | blob | blame | history
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