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(parent: f6f7233) | patch
disas/riscv: Add support for XThead* instructions
authorChristoph Müllner <christoph.muellner@vrull.eu>
Mon, 12 Jun 2023 11:10:34 +0000 (13:10 +0200)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 10 Jul 2023 12:29:14 +0000 (22:29 +1000)
commit318df7238b9f842af96aad01ec183012c8fecab9
tree7a1a7c1e60875c973c7010443f6103b8c800e220tree | snapshot
parentf6f72338d80ec6f15a6b18643797bc10901aadf3commit | diff
disas/riscv: Add support for XThead* instructions

Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
disas/meson.build diff | blob | blame | history
disas/riscv-xthead.c [new file with mode: 0644] blob
disas/riscv-xthead.h [new file with mode: 0644] blob
disas/riscv.c diff | blob | blame | history
disas/riscv.h diff | blob | blame | history
target/riscv/cpu_cfg.h diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git