]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
authorFrank Chang <frank.chang@sifive.com>
Tue, 18 Jan 2022 01:45:14 +0000 (09:45 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 21 Jan 2022 05:52:56 +0000 (15:52 +1000)
commit32e579b8c510f0c8d7023d87b0cfacf782cb4a62
treeff7e162e9591c021e7583c05afea7c30e63ea611
parentbfefe406b7666bfc624bf54820aa14bd43838dc5
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/cpu_helper.c
target/riscv/csr.c
target/riscv/translate.c