]> git.ipfire.org Git - thirdparty/gcc.git/commit
rtl-optimization/118662 - wrong combination of vector sign-extends
authorRichard Biener <rguenther@suse.de>
Mon, 27 Jan 2025 09:49:51 +0000 (10:49 +0100)
committerRichard Biener <rguenth@gcc.gnu.org>
Mon, 27 Jan 2025 12:31:35 +0000 (13:31 +0100)
commit343e1083eb9f57e05c0caba195f118ef2e95cc40
tree6f83a82c50de3d4d2361edb8668eaff126d2edc7
parent52366356fe7b638f66c4011b8a61fb6c22b08087
rtl-optimization/118662 - wrong combination of vector sign-extends

The following fixes an issue in the RTL combiner where we correctly
combine two vector sign-extends with a vector load

Trying 7, 9 -> 10:
    7: r106:V4QI=[r119:DI]
      REG_DEAD r119:DI
    9: r108:V4HI=sign_extend(vec_select(r106:V4QI#0,parallel))
   10: r109:V4SI=sign_extend(vec_select(r108:V4HI#0,parallel))
      REG_DEAD r108:V4HI

to

modifying insn i2     9: r109:V4SI=sign_extend([r119:DI])

but since r106 is used we wrongly materialize it using a subreg:

modifying insn i3    10: r106:V4QI=r109:V4SI#0

which of course does not work for modes with more than one component,
specifically vector and complex modes.

PR rtl-optimization/118662
* combine.cc (try_combine): When re-materializing a load
from an extended reg by a lowpart subreg make sure we're
not dealing with vector or complex modes.

* gcc.dg/torture/pr118662.c: New testcase.
gcc/combine.cc
gcc/testsuite/gcc.dg/torture/pr118662.c [new file with mode: 0644]