]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: add shcounterenw
authorDaniel Henrique Barboza <dbarboza@ventanamicro.com>
Wed, 18 Dec 2024 11:40:20 +0000 (08:40 -0300)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 18 Jan 2025 23:44:34 +0000 (09:44 +1000)
commit3739732e755d84859fc2278ae3fff7d3869507b5
tree6b333f788c315a00e544431c2e0b581b10d558b2
parente9952b3631b97f35d06052e0f3ec7ce812c9b539
target/riscv: add shcounterenw

shcounterenw is defined in RVA22 as:

"For any hpmcounter that is not read-only zero, the corresponding bit in
hcounteren must be writable."

This is always true in TCG so let's claim support for it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241218114026.1652352-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
tests/data/acpi/riscv64/virt/RHCT