RISC-V: Vector pesudoinsns with x0 operand to use imm 0

RISC-V: Vector pesudoinsns with x0 operand to use imm 0

A couple of Vector pseudoinstructions use x0 scalar which could be
inefficient on wider uarches due to regfile crossing.

Instead use the imm 0 form, which should be functionally equivalent.

 pseudoinsn            orig insn with x0     this patch
 --------------------  --------------------  -------------------
 vneg.v vd,vs          vrsub.vx vd,vs,x0     vrsub.vi vd,vs,0
 vncvt.x.x.w vd,vs,vm  vnsrl.wx vd,vs,x0,vm  vnsrl.wi vd,vs,0,vm
 vwcvt.x.x.v vd,vs,vm  vwadd.vx vd,vs,x0,vm  (imm not supported)

gcc/ChangeLog:
	* config/riscv/vector.md: vncvt substitute vnsrl.
	vnsrl with x0 replace with immediate 0.
	vneg substitute vrsub.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Change
	expected pattern.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/convert-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/convert-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/neg-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/base/simplify-vdiv.c: Ditto.
	* gcc.target/riscv/rvv/base/unop_v_constraint-1.c: Ditto.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>